Semiconductor device and manufacturing method of the same

• US 8,241,948 B2
• Filed: 06/03/2010
• Issued: 08/14/2012
• Est. Priority Date: 06/30/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujii, Gen
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US12/792,816
• Publication Number:
  US 20100240173A1
• Time in Patent Office: 803 Days
• Field of Search: 438/678, 438/677, 438/647, 438/610, 438/641, 438/401, 438/686, 438/674, 438/104, 257/E21.161, 257/E21.171, 257/E21.174, 257/E21.479, 257/E21.476, 427/301, 427/427.1, 427/466, 427/304, 430/315, 430/324, 205/105
• US Class Current: 438/104
• CPC Class Codes: C23C 18/1216 Metal oxides C23C18/1212 takes precedence
• CPC Class Codes: C23C 18/14 Decomposition by irradiation, e.g. photolysis, particle radiation or by mixed irradiation sources
• CPC Class Codes: C23C 18/1608 from pretreatment step, i.e. selective pre-treatment
• CPC Class Codes: C23C 18/165 Multilayered product layered product B32B
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1893 with use of organic or inorganic compounds other than metals, first
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.

Claims

1. A manufacturing method of a semiconductor device, comprising the steps of:

selectively forming a first material including an amino group over a substrate by discharging a composition including the first material including an amino group;

immersing the first material including an amino group in a solution including a first plating catalyst material so as to form the first plating catalyst material over the first material including an amino group;

immersing the first plating catalyst material in a plating solution including a first metal material so as to form a gate electrode layer over a surface of the first material including an amino group;

forming a gate insulating layer over the gate electrode layer;

selectively forming a source or drain electrode layer over the gate insulating layer by a droplet-discharge method; and

forming a semiconductor layer over the source or drain electrode layer,

wherein the semiconductor layer comprises zinc oxide.

2. The manufacturing method of a semiconductor device according to claim 1, wherein an ITO thin film, a gold thin film, or a Ti thin film is formed as at least one of the gate electrode layer, the source electrode layer and the drain electrode layer.

3. The manufacturing method of a semiconductor device according to claim 1, wherein a Y_zO_x, an Al₂O₃, a TiO₂, or a stacked layer thereof is used for the gate insulating layer.

4. A manufacturing method of a semiconductor device, comprising the steps of:

selectively forming a first material including an amino group over a substrate by discharging a composition including the first material including an amino group;

immersing the first material including an amino group in a solution including a first plating catalyst material so as to form the first plating catalyst material over the first material including an amino group;

immersing the first plating catalyst material in a plating solution including a first metal material so as to form a gate electrode layer over a surface of the first material including an amino group;

forming a gate insulating layer over the gate electrode layer;

selectively forming a source or drain electrode layer over the gate insulating layer by a droplet-discharge method; and

forming a semiconductor layer over the source or drain electrode layer,

wherein the semiconductor layer comprises zinc oxide, indium and gallium.

5. The manufacturing method of a semiconductor device according to claim 4, wherein an ITO thin film, a gold thin film, or a titanium thin film is formed as at least one of the gate electrode layer, the source electrode layer and the drain electrode layer.

6. The manufacturing method of a semiconductor device according to claim 4, wherein a Y_zO_x, an Al₂O₃, a TiO₂, or a stacked layer thereof is used for the gate insulating layer.

7. A manufacturing method of a semiconductor device, comprising the steps of:

selectively forming a first material including an amino group over a substrate by discharging a composition including the first material including an amino group;

immersing the first material including an amino group in a solution including a first plating catalyst material so as to form the first plating catalyst material over the first material including an amino group;

immersing the first plating catalyst material in a plating solution including a first metal material so as to form a gate electrode layer over a surface of the first material including an amino group;

forming a gate insulating layer over the gate electrode layer;

selectively forming a second material including an amino group over the gate insulating layer by discharging a composition including the second material including an amino group;

immersing the second material including an amino group in a solution including a second plating catalyst material so as to form the second plating catalyst material over the second material including an amino group; and

immersing the second plating catalyst material in a plating solution including a second metal material so as to form a source or drain electrode layer over a surface of the second material including an amino group; and

forming a semiconductor layer over the source or drain electrode layer,

wherein the semiconductor layer comprises zinc oxide.

8. The manufacturing method of a semiconductor device according to claim 7,

wherein pH of each of the solution including the first plating catalyst material and the solution including the second plating catalyst material is adjusted in a range of 3 to 6.

9. The manufacturing method of a semiconductor device according to claim 7, wherein an ITO thin film, a gold thin film, or a Ti thin film is formed as at least one of the gate electrode layer, the source electrode layer and the drain electrode layer.

10. The manufacturing method of a semiconductor device according to claim 7, wherein palladium, platinum, rhodium, or gold is used as at least one of the first plating catalyst material and the second plating catalyst material.

11. The manufacturing method of a semiconductor device according to claim 7, wherein a Y_zO_x, an Al₂O₃, a TiO₂, or a stacked layer thereof is used for the gate insulating layer.

12. A manufacturing method of a semiconductor device, comprising the steps of:

selectively forming a first material including an amino group over a substrate by discharging a composition including the first material including an amino group;

immersing the first material including an amino group in a solution including a first plating catalyst material so as to form the first plating catalyst material over the first material including an amino group;

immersing the first plating catalyst material in a plating solution including a first metal material so as to form a gate electrode layer over a surface of the first material including an amino group;

forming a gate insulating layer over the gate electrode layer;

selectively forming a second material including an amino group over the gate insulating layer by discharging a composition including the second material including an amino group;

immersing the second material including an amino group in a solution including a second plating catalyst material so as to form the second plating catalyst material over the second material including an amino group; and

immersing the second plating catalyst material in a plating solution including a second metal material so as to form a source or drain electrode layer over a surface of the second material including an amino group; and

forming a semiconductor layer over the source or drain electrode layer,

wherein the semiconductor layer comprises zinc oxide, indium and gallium.

13. The manufacturing method of a semiconductor device according to claim 12,

wherein pH of each of the solution including the first plating catalyst material and the solution including the second plating catalyst material is adjusted in a range of 3 to 6.

14. The manufacturing method of a semiconductor device according to claim 12, wherein an ITO thin film, a gold thin film, or a titanium thin film is formed as at least one of the gate electrode layer, the source electrode layer and the drain electrode layer.

15. The manufacturing method of a semiconductor device according to claim 12, wherein palladium, platinum, rhodium, or gold is used as at least one of the first plating catalyst material and the second plating catalyst material.

16. The manufacturing method of a semiconductor device according to claim 12, wherein a Y_zO_x, an Al₂O₃, a TiO₂, or a stacked layer thereof is used for the gate insulating layer.