Semiconductor chip with passivation layer comprising metal interconnect and contact pads

• US 8,242,601 B2
• Filed: 05/13/2009
• Issued: 08/14/2012
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chiu-Ming, Chou, Chien-Kang, Lin, Ching-San, Lin, Mou-Shiung
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): KARIMY, MOHAMMAD TIMOR
• Application Number:
  US12/464,896
• Publication Number:
  US 20090218687A1
• Time in Patent Office: 1,189 Days
• Field of Search: 257/758, 257/737, 257/E23.142, 257/288, 257/503
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01076 Osmium [Os]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15788 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said silicon substrate and said first metal layer, wherein said second metal layer comprises electroplated copper, wherein said second metal layer comprises a first contact pad, a second contact pad and a third contact pad that are aligned in a first line;

a dielectric layer between said first and second metal layers;

a passivation layer on said second metal layer and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over said first contact pad, wherein a second opening in said passivation layer is over said second contact pad, and wherein a third opening in said passivation layer is over said third contact pad;

a patterned metal layer on said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a fourth contact pad on said first contact pad, wherein said fourth contact pad is connected to said first contact pad through said first opening, a fifth contact pad connected to said second contact pad through said second opening, wherein said fifth contact pad is not vertically over said second contact pad, and a sixth contact pad on said third contact pad, wherein said sixth contact pad is connected to said third contact pad through said third opening;

a first metal bump on said fourth contact pad and vertically over said first contact pad;

a second metal bump on said fifth contact pad and not vertically over said second contact pad; and

a third metal bump on said sixth contact pad and vertically over said third contact pad, wherein said third metal bump comprises a single metal layer, having a height between 8 and 50 micrometers, contacting said sixth contact pad, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line.

2. The semiconductor chip of claim 1 further comprising a polymer layer on said passivation layer, wherein said patterned metal layer is further on said polymer layer.

3. The semiconductor chip of claim 2, wherein said polymer layer has a thickness between 1 and 30 micrometers.

4. The semiconductor chip of claim 1, wherein said nitride has a thickness between 0.05 and 0.5 micrometers.

5. The semiconductor chip of claim 1, wherein said nitride comprises silicon oxynitride.

6. The semiconductor chip of claim 1, wherein said single metal layer of said third metal bump comprises a gold layer.

7. The semiconductor chip of claim 1, wherein said height is between 10 and 30 micrometers.

8. The semiconductor chip of claim 1, wherein said third metal bump is configured to be connected to a contact pad of a printed circuit board.

9. The semiconductor chip of claim 1, wherein said third metal bump is configured to be connected to a contact pad of a flexible substrate.

10. The semiconductor chip of claim 1, wherein said third metal bump is configured to be connected to a contact pad of a glass substrate.

11. A semiconductor chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said silicon substrate and said first metal layer, wherein said second metal layer comprises electroplated copper, wherein said second metal layer comprises a first contact pad, a second contact pad and a third contact pad that are aligned in a first line;

a dielectric layer between said first and second metal layers;

a passivation layer on said second metal layer and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over said first contact pad, wherein a second opening in said passivation layer is over said second contact pad, and wherein a third opening in said passivation layer is over said third contact pad;

a patterned metal layer on said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first metal trace over said passivation layer, wherein said first metal trace is connected to said first contact pad through said first opening, a fourth contact pad connected to said first contact pad through said first metal trace, wherein said fourth contact pad is not vertically over said first contact pad, a second metal trace over said passivation layer, wherein said second metal trace is connected to said second contact pad through said second opening, a fifth contact pad connected to said second contact pad through said second metal trace, wherein said fifth contact pad is not vertically over said second contact pad, a third metal trace over said passivation layer, wherein said third metal trace is connected to said third contact pad through said third opening, and a sixth contact pad connected to said third contact pad through said third metal trace, wherein said sixth contact pad is not vertically over said third contact pad, wherein said second metal trace passes through a gap between said fourth and sixth contact pads;

a first metal bump on said fourth contact pad, wherein said first metal bump is not vertically over said first contact pad;

a second metal bump on said fifth contact pad, wherein said second metal bump is not vertically over from said second contact pad; and

a third metal bump on said sixth contact pad, wherein said third metal bump is not vertically over said third contact pad, wherein said third metal bump comprises a single metal layer, having a height between 8 and 50 micrometers, contacting said sixth contact pad.

12. The semiconductor chip of claim 11 further comprising a polymer layer on said passivation layer, wherein said patterned metal layer is further on said polymer layer.

13. The semiconductor chip of claim 12, wherein said polymer layer has a thickness between 1 and 30 micrometers.

14. The semiconductor chip of claim 11, wherein said nitride has a thickness between 0.05 and 0.5 micrometers.

15. The semiconductor chip of claim 11, wherein said nitride comprises silicon oxynitride.

16. The semiconductor chip of claim 11, wherein said single metal layer of said third metal bump comprises a gold layer.

17. The semiconductor chip of claim 11, wherein said height is between 10 and 30 micrometers.

18. The semiconductor chip of claim 11, wherein said third metal bump is configured to be connected to a contact pad of a printed circuit board.

19. The semiconductor chip of claim 11, wherein said third metal bump is configured to be connected to a contact pad of a flexible substrate.

20. The semiconductor chip of claim 11, wherein said third metal bump is configured to be connected to a contact pad of a glass substrate.

21. The semiconductor chip of claim 11, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line.

22. A semiconductor chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said silicon substrate and said first metal layer, wherein said second metal layer comprises electroplated copper, wherein said second metal layer comprises a first contact pad, a second contact pad, a third contact pad and a fourth contact pad;

a dielectric layer between said first and second metal layers;

a separating layer on said second metal layer and over said dielectric layer, wherein a first opening in said separating layer is over said first contact pad, wherein said first opening has a largest transverse dimension between 0.1 and 30 micrometers, wherein a second opening in said separating layer is over said second contact pad, wherein a third opening in said separating layer is over said third contact pad, and wherein a fourth opening in said separating layer is over said fourth contact pad;

a patterned metal layer on said first, second, third and fourth contact pads and on said separating layer, wherein there is no polymer layer between said patterned metal layer and said separating layer, wherein said patterned metal layer comprises a fifth contact pad on said first contact pad, wherein said fifth contact pad is connected to said first contact pad through said first opening, a sixth contact pad connected to said second contact pad through said second opening, wherein said sixth contact pad is not vertically over said second contact pad, a seventh contact pad on said third contact pad, wherein said seventh contact pad is connected to said third contact pad through said third opening, and an eighth contact pad connected to said fourth contact pad through said fourth opening, wherein said eighth contact pad is not vertically over said fourth contact pad;

a first metal bump on said fifth contact pad and vertically over said first contact pad;

a second metal bump on said sixth contact pad, wherein said second metal bump is not vertically over said second contact pad;

a third metal bump on said seventh contact pad and vertically over said third contact pad, wherein said first and third metal bumps are aligned in a first line; and

a fourth metal bump on said eighth contact pad, wherein said fourth metal bump is not vertically over said fourth contact pad, wherein said second and fourth metal bumps are aligned in a second line substantially parallel with said first line, wherein said fourth metal bump has a height between 8 and 50 micrometers.

23. The semiconductor chip of claim 22, wherein there is no metal bump on a point on said first line, wherein said point is at an intersection of said first line and a third line that is perpendicular to said first line and extends to said second metal bump.

24. The semiconductor chip of claim 22, wherein said separating layer comprises an oxynitride layer.

25. The semiconductor chip of claim 22, wherein said fourth metal bump is configured to be connected to a contact pad of a printed circuit board.

26. The semiconductor chip of claim 22, wherein said fourth metal bump comprises gold.

27. The semiconductor chip of claim 22, wherein said separating layer comprises an oxide layer having a thickness between 0.5 and 3 micrometers.

28. The semiconductor chip of claim 22, wherein said separating layer comprises a nitride layer.

29. A semiconductor chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said silicon substrate and said first metal layer, wherein said second metal layer comprises electroplated copper, wherein said second metal layer comprises a first contact pad, a second contact pad, a third contact pad and a fourth contact pad;

a dielectric layer between said first and second metal layers;

a separating layer on said second metal layer and over said dielectric layer, wherein a first opening in said separating layer is over said first contact pad, wherein said first opening has a largest transverse dimension between 0.1 and 30 micrometers, wherein a second opening in said separating layer is over said second contact pad, wherein a third opening in said separating layer is over said third contact pad, and wherein a fourth opening in said separating layer is over said fourth contact pad;

a patterned metal layer on said first, second, third and fourth contact pads and on said separating layer, wherein there is no polymer layer between said patterned metal layer and said separating layer, wherein said patterned metal layer comprises a fifth contact pad connected to said first contact pad through said first opening, wherein said fifth contact pad is not vertically over said first contact pad, a sixth contact pad connected to said second contact pad through said second opening, wherein said sixth contact pad is not vertically over said second contact pad, a seventh contact pad connected to said third contact pad through said third opening, wherein said seventh contact pad is not vertically over said third contact pad, and an eighth contact pad connected to said fourth contact pad through said fourth opening, wherein said eighth contact pad is not vertically over said fourth contact pad;

a first metal bump on said fifth contact pad, wherein said first metal bump is not vertically over said first contact pad;

a second metal bump on said sixth contact pad, wherein said second metal bump is not vertically over said second contact pad;

a third metal bump on said seventh contact pad, wherein said third metal bump is not vertically over said third contact pad, wherein said first and third metal bumps are aligned in a first line, wherein from a top perspective view, a second line connecting said second metal bump to said second metal pad passes through a gap between said first and third metal bumps; and

a fourth metal bump on said eighth contact pad, wherein said fourth metal bump is not vertically over said fourth contact pad, wherein said second and fourth metal bumps are aligned in a third line substantially parallel with said first line, wherein said fourth metal bump has a height between 8 and 50 micrometers.

30. The semiconductor chip of claim 29, wherein said separating layer comprises an oxynitride layer.

31. The semiconductor chip of claim 29, wherein said fourth metal bump is configured to be connected to a contact pad of a printed circuit board.

32. The semiconductor chip of claim 29, wherein said fourth metal bump comprises gold.

33. The semiconductor chip of claim 29, wherein said separating layer comprises a nitride layer.