Method and apparatus for tuning phase of clock signal
First Claim
1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising:
- a clock signal receiver configured to receive the main clock signal and the data clock signal; and
a phase tuner configured to;
generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal,generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another,compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and output a phase detection signal, andcompare a phase of a signal selected, based on the phase detection signal, from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and output a comparison result.
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Abstract
A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.
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Citations
16 Claims
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1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising:
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a clock signal receiver configured to receive the main clock signal and the data clock signal; and a phase tuner configured to; generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal, generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another, compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and output a phase detection signal, and compare a phase of a signal selected, based on the phase detection signal, from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and output a comparison result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory controller for controlling at least one memory apparatus, the memory controller comprising:
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a clock signal generator configured to generate a main clock signal having a predetermined frequency and a data clock signal having a frequency different from the predetermined frequency of the main clock signal; a clock transmitter configured to transmit the main clock signal and the data clock signal to a first memory apparatus; a command/address transmitter configured to transmit a command and an address to the first memory apparatus in response to the main clock signal; and a data transceiver configured to transmit and receive data in response to the data clock signal, wherein the memory controller adjusts a phase of the data clock signal by a predetermined phase step based on a comparison result fed back from the first memory apparatus and transmits a phase-adjusted data clock signal to the first memory apparatus, and wherein the comparison result is signal generated by comparing a first frequency-divided clock signal, which is generated by dividing a frequency of the data clock signal with the main clock signal. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification