Semiconductor device with additional power supply paths

• US 8,243,465 B2
• Filed: 02/18/2010
• Issued: 08/14/2012
• Est. Priority Date: 02/18/2009
• Status: Expired due to Fees

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Itaya, Satoshi, Isa, Satoshi, Katagiri, Mitsuaki, Sasaki, Dai
• Primary Examiner(s): Thompson, Timothy
• Assistant Examiner(s): MILAKOVICH, NATHAN J
• Application Number:
  US12/707,996
• Publication Number:
  US 20100208443A1
• Time in Patent Office: 908 Days
• Field of Search: 361/783, 361/735, 361/780, 361/790, 361/301.4, 257/686
• US Class Current: 361/772
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/181 : associated with surface mounted components

Abstract

A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C_1d or first ground wiring 40C_1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C_2d and second ground wiring 40C_2s, which is extended in the same direction as with DQ system signal wiring 40C_DQ, forms a feedback current path. Second power source wiring 40C_2d and second ground wiring 40C_2s are disposed adjacent to DQ system signal wiring 40C_DQ.

Claims

1. A device, comprising:

a package substrate comprising a first power supply terminal, a second power supply terminal, a signal terminal, and a plurality of conductive layers;

a first semiconductor chip located above the package substrate, and the semiconductor chip comprising a first circuit operating on a first power supply voltage, a second circuit operating on a second power supply voltage and generating an output signal, a first pad supplying the first circuit with a first power supply potential as one of potentials of the first power supply voltage and a second pad supplying the second circuit with a second power supply potential as one of potentials of the second power supply voltage, a signal pad receiving the output signal from the second circuit;

a first additional substrate located above the first semiconductor chip, the first additional substrate comprising a first wiring layer formed on an opposite side to the first semiconductor chip;

a first power supply path electrically connecting the first power supply terminal of the package substrate to the first wiring layer of the first additional substrate;

a second power supply path electrically connecting the first wiring layer of the first additional substrate to the first pad of the first semiconductor chip, the second conductive path being free from including any one of the conductive layers of the package substrate between the first wiring layer of the first additional substrate and the first pad of the first semiconductor chip;

a third power supply path electrically connecting the second power supply terminal of the package substrate to the second pad of the first semiconductor chip; and

a signal path electrically connecting the signal terminal of the package substrate to the signal pad of the first semiconductor chip.

2. The device according to claim 1, wherein the signal path is elongated in parallel to the third power supply path.

3. The device according to claim 1, wherein the package substrate comprises third and fourth power supply terminals, the first semiconductor chip comprises a third pad supplying the first circuit with a first ground potential as the other of the potentials of the first power supply voltage and a fourth pad supplying the second circuit with a second ground potential as the other of the potentials of the second power supply voltage, and the device further comprises:

a second additional substrate located above the first semiconductor chip, the second additional substrate comprises a second wiring layer formed on an opposite side to the first semiconductor chip;

a fifth power supply path electrically connecting the third power supply terminal of the package substrate to the second wiring layer of the second additional substrate;

a sixth power supply path electrically connecting the second wiring layer of the second additional substrate to the third pad of the first semiconductor chip, the sixth conductive path being free from including any one of the conductive layers of the package substrate between the second wiring layer of the second additional substrate and the third pad of the first semiconductor chip; and

a seventh power supply path electrically connecting the fourth power supply terminal of the package substrate to the fourth pad of the first semiconductor chip.

4. The device according to claim 3, wherein the second additional substrate is mounted on the first additional substrate at the opposite side to the first semiconductor chip of the first additional substrate.

5. The device according to claim 3, wherein the first additional substrate and the second additional substrate are mounted on the first semiconductor chip and arranged adjacently to and separately from each other.

6. A device, comprising:

a package substrate including first, second, and third connection lands formed on a first surface thereof and a plurality of conductive layers, the first and second connection lands being supplied respectively with a first and second power voltages;

a semiconductor chip mounted on the first surface of the package substrate and including first and second power supply pads, a peripheral circuit, a memory cell array and an output circuit, the peripheral circuit and the memory cell array operating on the first power voltage supplied through the first power supply pad, the output circuit operating on the second power voltage supplied through the second power supply pad and generating an output signal, and an output pad receiving the output signal from the output circuit;

a first additional substrate mounted on the semiconductor chip and including a first conductive layer;

a first power supply wiring connecting the first connection land of the package substrate to the first conductive layer of the first additional substrate so that the first conductive layer of the first additional substrate is supplied with the first power supply voltage;

a second power supply wiring connecting the first conductive layer of the first additional substrate to the first power supply pad of the semiconductor chip so that the first power supply pad of the semiconductor chip is supplied with the first power voltage without an interventions of any one of the conductive layers of the package substrate between the first conductive layer of the first additional substrate and the first power supply pad of the semiconductor chip;

a third power supply wiring connecting the second power supply pad of the semiconductor chip to the second connection land of the package substrate so that the second power supply pad of the semiconductor chip is supplied with the second power voltage, and the second power supply pad being free from connecting the first conductive layer of the first additional substrate; and

a signal wiring connecting the output pad of the semiconductor chip to the third connection land of the package substrate so that the output pad of the semiconductor chip supplies the output signal to the third connection land of the package substrate.

7. The device according to claim 6, wherein the first power supply pad is free from connecting to the first connection lands.

8. The device according to claim 6, wherein the package substrate includes fourth and fifth connection lands formed on the first surface thereof, the fourth and fifth connection lands being supplied respectively with a first and second ground voltage,

wherein the semiconductor chip includes first and second ground pads, the peripheral circuit and the memory cell array operating on the first ground voltage supplied through the first ground pad, and the output circuit operating on the second ground voltage supplied through the second ground pad, and the device further comprises:

a second additional substrate mounted on the semiconductor chip and including a second conductive layer on a third surface thereof;

a fourth power supply wiring connecting the third fourth connection land of the package substrate to the second conductive layer of the second additional substrate so that the second conductive layer of the second additional substrate is supplied with the first ground voltage;

a fifth power supply wiring connecting the second conductive layer of the second additional substrate to the first ground pad of the semiconductor chip so that the first ground pad of the semiconductor chip is supplied with the first ground voltage without an intervention of any one of the conductive layers of the package substrate between the second conductive layer of the second additional substrate and the first ground pad of the semiconductor chip; and

a sixth wiring connecting the second ground pad of the semiconductor chip to the fifth connection land of the package substrate so that the second ground pad of the semiconductor chip is supplied with the second ground voltage, and the second ground pad being free from connecting the second conductive layer of the second additional substrate.

9. The device according to claim 8, wherein the first power supply pad of the semiconductor chip is free from connecting to the first connection lands and the first ground pad of the semiconductor chip is free from connection to the third connection land.

10. The device according to claim 6, wherein the third power supply wiring and the signal wiring are elongated in parallel to each other.

11. A device, comprising:

a package substrate comprising a first power supply terminal and a second power supply terminal and a signal terminal;

a first semiconductor chip located above the package substrate, and the semiconductor chip comprising a first circuit operating on a first power supply voltage, a second circuit operating on a second power supply voltage and generating an output signal, a first pad supplying the first circuit with a first power supply potential as one of potentials of the first power supply voltage and a second pad supplying the second circuit with a second power supply potential as one of potentials of the second power supply voltage, a signal pad receiving the output signal from the second circuit;

a first additional substrate located above the first semiconductor chip, the first additional substrate comprising a first wiring layer formed on an opposite side to the first semiconductor chip, the first wiring layer including a first connection portion and a second connection portion that is continuous with the first connection portion;

a first power supply path comprising a first end portion that is in contact with the first power supply terminal of the package substrate and a second end portion that is in contact with the first connection portion of the first wiring layer of the first additional substrate;

a second power supply path comprising a third end portion that is in contact with the first pad of the first semiconductor chip and a fourth end portion that is in contact with the second connection portion of the first wiring layer of the first additional substrate;

a third power supply path comprising a fifth end portion that is in contact with the second power supply terminal of the package substrate and sixth end portion that is in contact with the second pad of the first semiconductor chip; and

a signal path comprising a seventh end portion that is in contact with the signal terminal of the package substrate and an eighth end portion that is in contact with the signal pad of the first semiconductor chip.

12. The device according to claim 11, wherein the signal path is elongated in parallel to the third power supply path.

13. The device according to claim 11,

wherein the package substrate comprises third and fourth power supply terminals, the first semiconductor chip comprises a third pad supplying the first circuit with a first ground potential as the other of the potentials of the first power supply voltage and a fourth pad supplying the second circuit with a second ground potential as the other of the potentials of the second power supply voltage, and

wherein the device further comprises:

a second additional substrate located above the first semiconductor chip, the second additional substrate comprises a second wiring layer formed on an opposite side to the first semiconductor chip, the second wiring layer including a third connection portion and a fourth connection portion that is continuous with the third connection portion;

a fourth power supply path comprising a ninth end portion that is in contact with the third power supply terminal of the package substrate and a tenth end portion that is in contact with the third connection portion of the second wiring layer of the second additional substrate;

a fifth power supply path comprising an eleventh end portion that is in contact with the third pad of the first semiconductor chip and a twelfth end portion that is in contact with the fourth connection portion of the second wiring layer of the second additional substrate; and

a sixth power supply path comprising a thirteenth end portion that is in contact with the fourth power supply terminal of the package substrate and fourteenth end portion that is in contact with the fourth pad of the first semiconductor chip.

14. The device according to claim 13, wherein the second additional substrate is mounted on the first additional substrate at the opposite side to the first semiconductor chip of the first additional substrate.

15. The device according to claim 13, wherein the first and second substrate is mounted on the first semiconductor chip and arranged adjacently to and separately from each other.