Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

• US 8,243,499 B2
• Filed: 05/26/2011
• Issued: 08/14/2012
• Est. Priority Date: 08/22/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): PHAM, HAI Q
• Application Number:
  US13/116,924
• Publication Number:
  US 20110228591A1
• Time in Patent Office: 446 Days
• Field of Search: 365/148, 365/185.08, 365/185.18, 365/163
• US Class Current: 365/148
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 : Material having simple binary metal oxide structure
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 63/10 : Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/32 : of the bipolar type
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 : between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Claims

1. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory, said method comprising:

storing data in a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory; and

storing data in a resistance change element electrically connected to one of said first and second regions by configuring the resistance change element in one of a plurality of resistivity states, wherein each of said resistivity states corresponds to a different data value, respectively;

wherein said capacitorless transistor and said resistance change element are included in a memory cell, said cell comprising said floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type;

first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;

said first and second regions being located such that at least a portion of the floating body is located between said first and second locations; and

a gate positioned between said first and second regions and adjacent said floating body region.

2. The method of claim 1, wherein said resistance change element is configurable to a high resistivity state and a low resistivity state, respectively.

3. The method of claim 1, wherein said memory cell further comprises a buried layer in a substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

wherein said capacitorless transistor of said memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration.

4. The method of claim 3, further comprising a substrate terminal connected to said substrate beneath said buried layer;

said resistive change element connected to one of said first and second regions;

a source line terminal electrically connected to one of said first region and second regions;

a bit line terminal electrically connected to the other of said first and second regions, wherein one of said source line and said bit line is connected to said one of said first and second regions by connection to said resistive change element;

a word line terminal connected to said gate; and

a buried well terminal electrically connected to said buried layer.

5. The method of claim 4, wherein said source line terminal is connected to said resistance change element which is in turn connected to said second region, said method further comprising shadowing data stored in said floating body to said resistance change element.

6. The method of claim 5, wherein said shadowing process is performed non-algorithmically.

7. The method of claim 5, wherein when said floating body stores a positive potential, resulting electric current flowing through said resistance change element changes said resistance change material from a low resistivity state to a high resistivity state, and said resistance change material remains in said high resistivity state when voltages to said terminals are discontinued;

and

wherein when said floating body stores a neutral or negative potential, the capaitorless transistor is turned off and electric current does not flow through said resistance change element, whereby said resistance change element remains in said low resistivity state, and said resistance change material remains in said low resistivity state when voltages to said terminals are discontinued.

8. The method of claim 4, wherein said source line terminal is connected to said resistance change element which is in turn connected to said second region, said method further comprising, after discontinuance of power said cell and upon restoring power to said cell, restoring data stored on said resistance change element to said floating body, wherein said restoring data is performed by:

applying a negative voltage to said source line terminal;

applying a positive voltage to said bit line terminal;

applying a negative voltage to said word line terminal;

applying a low positive voltage to said buried well terminal; and

applying a substantially neutral voltage to said substrate terminal.

9. The method of claim 8, wherein said restoring data process is performed non-algorithmically.

10. The method of claim 8, wherein when said resistance change element is in a high resistivity state, holes are injected into said floating body causing said floating body to store a positive potential;

and

wherein when said resistance change element is in a low resistivity state, holes are evacuated from said floating body causing said floating body to store a neutral potential.

11. The method of claim 10, said method further comprising, after restoring data stored in said floating body, resetting said resistance change element, wherein said resetting comprises resetting said resistance change element to a predetermined resistivity state.

12. The method of claim 11, wherein said resetting comprises:

applying a positive voltage to said source line terminal;

applying a substantially neutral voltage to said bit line terminal;

applying a neutral voltage or slightly positive voltage to said word line terminal;

applying a positive voltage to said buried well terminal; and

applying a substantially neutral voltage to said substrate terminal.

13. The method of claim 11, wherein said resetting comprises:

applying a substantially neutral voltage to said source line terminal;

applying a neutral voltage or slightly positive voltage to said word line terminal;

applying a positive voltage to said substrate terminal;

allowing said bit line terminal and said buried well terminal to float.

14. The method of claim 1, wherein said capacitorless transistor and said resistance change element are included in a memory cell, said cell comprising a silicon-on-insulator substrate, a substrate of said being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

a second region having said second conductivity type, said second region being spaced apart from said first region;

a buried insulator layer in said substrate below said first and second regions, spaced apart from said first and second regions and insulating a body region from said substrate, said body region formed between said first and second regions and said buried insulator layer, said body region having said first conductivity type and storing said data when power is applied to said cell; and

a gate positioned between said first and second regions and adjacent said body region;

wherein said resistive change element is connected to one of said first and second regions;

wherein said capacitorless transistor of said memory cell is configured to store a first data state which corresponds to a first charge in the body region as said in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration.

15. The method of claim 14, further comprising a substrate terminal connected to said substrate beneath said buried insulator layer;

said resistive change element connected to one of said first and second regions;

a source line terminal electrically connected to one of said first region and second regions;

a bit line terminal electrically connected to the other of said first and second regions, wherein one of said source line and said bit line is connected to said one of said first and second regions by connection to said resistive change element; and

a word line terminal connected to said gate.

16. The method of claim 15, wherein said source line terminal is connected to said resistance change element which is in turn connected to said second region, said method further comprising shadowing data stored in said floating body to said resistance change element, wherein said shadowing is performed by:

applying a positive voltage to said source line terminal;

applying a substantially neutral voltage to said bit line terminal;

applying a neutral voltage or slightly positive voltage to said word line terminal; and

applying a neutral or negative voltage to said substrate terminal.

17. The method of claim 15, wherein said source line terminal is connected to said resistance change element which is in turn connected to said second region, said method further comprising, after discontinuance of power to said cell and upon restoring power to said cell, restoring data stored on said resistance change element to said floating body, wherein said restoring data is performed by:

applying a negative voltage to said source line terminal;

applying a positive voltage to said bit line terminal;

applying a negative voltage to said word line terminal; and

applying a neutral or negative voltage to said substrate terminal.

18. The method of claim 17, wherein when said resistance change element is in a high resistivity state, holes are injected into said floating body causing said floating body to store a positive potential;

and

wherein when said resistance change element is in a low resistivity state, holes are evacuated from said floating body causing said floating body to store a neutral potential.

19. The method of claim 18, said method further comprising, after restoring data stored in said floating body, resetting said resistance change element, wherein said resetting comprises resetting said resistance change element to a predetermined resistivity state.

20. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory, said method comprising:

storing data in a capacitorless transistor of a memory cell having a floating body configured to store data as charge therein when power is applied to said memory; and

transferring data stored in said capacitorless transistor to a resistance change element in response to discontinuance of power to said memory cell, wherein said resistance change element is included in said memory cell.