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Non-volatile memory cell with metal capacitor

  • US 8,243,510 B2
  • Filed: 08/30/2006
  • Issued: 08/14/2012
  • Est. Priority Date: 08/30/2006
  • Status: Active Grant
First Claim
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1. A memory cell residing in a semiconductor chip, said memory cell comprising:

  • a non-volatile memory transistor comprising a floating gate;

    a control gate being capacitively coupled to said floating gate by a metal capacitor comprising interconnect metal formed in one metal level of said semiconductor chip over an interlayer dielectric;

    a metal interconnect coupling said metal capacitor and said floating gate, said metal interconnect formed in said one metal level;

    wherein a state of said non-volatile memory transistor is read through a readout transistor coupled to said floating gate of said non-volatile memory transistor and a select transistor in series with said readout transistor.

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