Non-volatile memory cell with metal capacitor
First Claim
Patent Images
1. A memory cell residing in a semiconductor chip, said memory cell comprising:
- a non-volatile memory transistor comprising a floating gate;
a control gate being capacitively coupled to said floating gate by a metal capacitor comprising interconnect metal formed in one metal level of said semiconductor chip over an interlayer dielectric;
a metal interconnect coupling said metal capacitor and said floating gate, said metal interconnect formed in said one metal level;
wherein a state of said non-volatile memory transistor is read through a readout transistor coupled to said floating gate of said non-volatile memory transistor and a select transistor in series with said readout transistor.
6 Assignments
0 Petitions
Accused Products
Abstract
According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a metal capacitor. The metal capacitor can be formed in one or more metal levels and in one embodiment is in a shape of a comb with multiple fingers. In one embodiment, the non-volatile memory transistor is an NMOS non-volatile memory transistor.
19 Citations
14 Claims
-
1. A memory cell residing in a semiconductor chip, said memory cell comprising:
-
a non-volatile memory transistor comprising a floating gate; a control gate being capacitively coupled to said floating gate by a metal capacitor comprising interconnect metal formed in one metal level of said semiconductor chip over an interlayer dielectric; a metal interconnect coupling said metal capacitor and said floating gate, said metal interconnect formed in said one metal level; wherein a state of said non-volatile memory transistor is read through a readout transistor coupled to said floating gate of said non-volatile memory transistor and a select transistor in series with said readout transistor. - View Dependent Claims (2, 3, 4)
-
-
5. A memory cell residing in a semiconductor chip, said memory cell comprising:
-
a non-volatile memory transistor comprising a floating gate; a control gate being capacitively coupled to said floating gate by a metal capacitor comprising interconnect metal formed in one metal level of said semiconductor chip over an interlayer dielectric; a metal interconnect coupling said metal capacitor and said floating gate, said metal interconnect formed in said one metal level; wherein said metal capacitor is situated to one side of said floating gate such that no portion of said metal capacitor is situated directly above said floating gate. - View Dependent Claims (6, 7, 8, 9)
-
-
10. An electronic system comprising:
a semiconductor chip comprising at least one memory cell, said at least one memory cell comprising; a non-volatile memory transistor comprising a floating gate; a control gate being capacitively coupled to said floating gate by a metal capacitor comprising interconnect metal formed in one metal level of said semiconductor chip over an interlayer dielectric; a metal interconnect coupling said metal capacitor and said floating gate, said metal interconnect formed in said one metal level; wherein a state of said non-volatile memory transistor is read through a readout transistor coupled to said floating gate of said non-volatile memory transistor and a select transistor in series with said readout transistor. - View Dependent Claims (11, 12, 13, 14)
Specification