Data processing apparatus
First Claim
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1. A data processing apparatus comprising:
- a binarization unit binarizing input data based on a threshold voltage and configured to output only a binary output from a single connection point between a drain of a PMOS transistor and a drain of a NMOS transistor;
a capture unit capturing data from the binary output binarized by the binarization unit;
a duty cycle detection unit detecting a duty cycle of the binary output; and
a control unit, implemented via a processor, controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit and configured to output only a single control signal directly into a gate of another PMOS transistor of the binarization unit, wherein a drain current value of the another PMOS transistor is varied in accordance with a change of the single control signal,wherein the duty cycle detection unit is configured to detect the duty cycle of the binary output from an average value of the binary output and pulse values when the binary output is at a high (H) level and at a low (L) level.
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Abstract
A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.
12 Citations
14 Claims
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1. A data processing apparatus comprising:
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a binarization unit binarizing input data based on a threshold voltage and configured to output only a binary output from a single connection point between a drain of a PMOS transistor and a drain of a NMOS transistor; a capture unit capturing data from the binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit, implemented via a processor, controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit and configured to output only a single control signal directly into a gate of another PMOS transistor of the binarization unit, wherein a drain current value of the another PMOS transistor is varied in accordance with a change of the single control signal, wherein the duty cycle detection unit is configured to detect the duty cycle of the binary output from an average value of the binary output and pulse values when the binary output is at a high (H) level and at a low (L) level. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing apparatus comprising:
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a binarization unit binarizing input data based on a threshold voltage and configured to output only a binary output from a single connection point between a drain of a PMOS transistor and a drain of a NMOS transistor; a capture unit capturing data from the binary output binarized by the binarization unit; a simulated pulse generation unit generating simulated pulses of the binary output to be captured in the capture unit; a duty cycle detection unit detecting a duty cycle of the simulated pulses generated by the simulated pulse generation unit; and a control unit, implemented via a processor, controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit and configured to output only a single control signal directly into a gate of another PMOS transistor of the binarization unit, wherein a drain current value of the another PMOS transistor is varied in accordance with a change of the single control signal, wherein the duty cycle detection unit is configured to detect the duty cycle of the simulated pulses of the binary output from an average value of the simulated pulses and pulse values when the simulated pulses are at a high (H) level and at a low (L) level. - View Dependent Claims (9, 10)
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11. A data processing apparatus comprising:
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a binarization unit binarizing input data based on a threshold voltage and configured to output only a binary output from a single connection point between a drain of a PMOS transistor and a drain of a NMOS transistor; a capture unit capturing data from the binary output binarized by the binarization unit; an average value detection unit detecting an average value of the binary output; and a control unit, implemented via a processor, controlling a level of the input data based on the average value detected by the average value detection unit and configured to output only a single control signal directly into a gate of another PMOS transistor of the binarization unit, wherein a drain current value of the another PMOS transistor is varied in accordance with a change of the single control signal, wherein a duty cycle of the binary output is detected from the average value of the binary output and pulse values when the binary output is at a high (H) level and at a low (L) level. - View Dependent Claims (12, 13, 14)
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Specification