Normalization of floating point operations in a programmable integrated circuit device

• US 8,244,789 B1
• Filed: 03/14/2008
• Issued: 08/14/2012
• Est. Priority Date: 03/14/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US12/048,379
• Time in Patent Office: 1,614 Days
• Field of Search: 708/497, 708552-553
• US Class Current: 708/497
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only

Abstract

A programmable integrated circuit device is programmed to normalize multiplication operations by examining the input or output values to determined the likelihood of overflow or underflow and then to adjust the input or output values accordingly. The examination of the inputs can include an examination of the number of adder stages feeding into the inputs, as well as a count of leading bits ahead of the first significant bit. Adjustment of an input can include shifting the mantissa by the leading bit count and adjusting the exponent accordingly, while adjustment of the output can include shifting the mantissa by the sum of the leading bit counts of the inputs and adjusting the exponent accordingly. Or the output can be examined to find its leading bit count and the output then can be adjusted by shifting the mantissa by the leading bit count and adjusting the exponent accordingly.

Claims

1. A method of configuring a programmable integrated circuit device to perform a floating point multiplication operation on multiplicand input values each formatted with a respective input mantissa/exponent pair, to provide an output value formatted with an output mantissa/exponent pair, said method comprising:

configuring logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation.

2. The method of claim 1 wherein said configuring logic of said programmable integrated circuit device to examine said values comprises configuring logic of said programmable integrated circuit device to examine said input values.

3. The method of claim 2 wherein:

said input and output mantissas have a number of overflow bits;

said configuring logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to, when said number of adder stages exceeds said number of overflow bits, right-shift said respective input mantissa and raise said respective input exponent accordingly.

4. The method of claim 2 wherein:

said configuring logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to count bits to a first significant bit in each said input to provide a respective bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift said respective input mantissa by said respective bit count and adjust said respective input exponent accordingly.

5. The method of claim 2 wherein:

said configuring logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to count bits to a first significant bit in each said input to provide a respective bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift said output mantissa by a sum of said respective bit counts and adjust said output exponent accordingly.

6. The method of claim 1 wherein said configuring logic of said programmable integrated circuit device to examine said values comprises configuring logic of said programmable integrated circuit device to examine said output values.

7. The method of claim 6 wherein:

said configuring logic of said programmable integrated circuit device to examine said output value to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to count bits to a first significant bit in said output to provide a bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift said output mantissa by said bit count and adjust said output exponent accordingly.

8. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values comprises configuring said logic to examine said values bit-by-bit; and

said configuring logic of said programmable integrated circuit device to adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow, comprises configuring said logic to make bit-by-bit adjustments.

9. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values comprises configuring said logic to examine said values by groups of bits; and

said configuring logic of said programmable integrated circuit device to adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow, comprises configuring said logic to make adjustments by groups of bits.

10. A programmable integrated circuit device configured to perform a floating point multiplication operation on multiplicand input values each formatted with a respective input mantissa/exponent pair, to provide an output value formatted with an output mantissa/exponent pair, said configured programmable logic device comprising:

logic configured to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

logic configured to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation.

11. The programmable integrated circuit device of claim 10 wherein said logic configured to examine said values is configured to examine said input values.

12. The programmable integrated circuit device of claim 11 wherein:

said input and output mantissas have a number of overflow bits;

said logic configured to examine said input values is configured to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said logic configured to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, is configured to, when said number of adder stages exceeds said number of overflow bits, right-shift said respective input mantissa and raise said respective input exponent accordingly.

13. The programmable integrated circuit device of claim 11 wherein:

said logic configured to examine said input values is configured to count bits to a first significant bit in each said input to provide a respective bit count; and

said logic configured to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, is configured to shift said respective input mantissa by said respective bit count and adjust said respective input exponent accordingly.

14. The programmable integrated circuit device of claim 11 wherein:

said logic configured to examine said input values to determine likelihood of overflow/underflow of said multiplication operation is configured to count bits to a first significant bit in each said input to provide a respective bit count; and

said logic configured to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, is configured to shift said output mantissa by a sum of said respective bit counts and adjust said output exponent accordingly.

15. The programmable integrated circuit device of claim 10 wherein said logic configured to examine said values is configured to examine said output values.

16. The programmable integrated circuit device of claim 15 wherein:

said logic configured to examine said output value to determine likelihood of overflow/underflow of said multiplication operation is configured to count bits to a first significant bit in said output to provide a bit count; and

said logic configured to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, is configured to shift said output mantissa by said bit count and adjust said output exponent accordingly.

17. The programmable integrated circuit device of claim 10 wherein:

said logic configured to examine said values is configured to examine said input values bit-by-bit; and

said logic configured to adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow is configured to make bit-by-bit adjustments.

18. The programmable integrated circuit device of claim 10 wherein:

said logic configured to examine said values is configured to examine said values by groups of bits; and

said logic configured to adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow shift said output mantissa and adjust said output exponent, is configured to make adjustments by groups of bits.

19. A machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform a floating point multiplication operation on multiplicand input values each formatted with a respective input mantissa/exponent pair, to provide an output value formatted with an output mantissa/exponent pair, said instructions comprising:

instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation.

20. The machine-readable data storage medium of claim 19 wherein said instructions to configure logic of said programmable integrated circuit device to examine said values comprise instructions to configure logic of said programmable integrated circuit device to examine said input values.

21. The machine-readable data storage medium of claim 20 wherein:

said input and output mantissas have a number of overflow bits;

said instructions to configure logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to, when said number of adder stages exceeds said number of overflow bits, right-shift said respective input mantissa and raise said respective input exponent accordingly.

22. The machine-readable data storage medium of claim 20 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in each said input to provide a respective bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to shift said respective input mantissa by said respective bit count and adjust said respective input exponent accordingly.

23. The machine-readable data storage medium of claim 20 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said input values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in each said input to provide a respective bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to shift said output mantissa by a sum of said respective bit counts and adjust said output exponent accordingly.

24. The machine-readable data storage medium of claim 19 wherein said instructions to configure logic of said programmable integrated circuit device to examine said values comprise instructions to configure logic of said programmable integrated circuit device to examine said output values.

25. The machine-readable data storage medium of claim 24 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said output value to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in said output to provide a bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust one of (a) at least one said respective input mantissa and input exponent, and (b) said output mantissa and output exponent, to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift said output mantissa by said bit count and adjust said output exponent accordingly.