Non-volatile memory and method with write cache partition management methods
First Claim
1. A nonvolatile memory, comprising:
- an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;
said array being partitioned into a first group of blocks and a second group of blocks;
a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel;
said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data;
said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data;
said second group of blocks having a capacity dynamically increased by allocation of blocks from said first group to said second group in response to a demand to increase the capacity;
a time stamp stored with each block, said time stamp having a value that is toggled when the block was programmed;
a free block list updated at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data.
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Abstract
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
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Citations
12 Claims
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1. A nonvolatile memory, comprising:
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an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together; said array being partitioned into a first group of blocks and a second group of blocks; a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel; said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data; said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; said second group of blocks having a capacity dynamically increased by allocation of blocks from said first group to said second group in response to a demand to increase the capacity; a time stamp stored with each block, said time stamp having a value that is toggled when the block was programmed; a free block list updated at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a nonvolatile memory having an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;
- a method of operating the nonvolatile memory, comprising;
partitioning the array into a first group of blocks and a second group of blocks; providing a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel; said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data; said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; and dynamically adjusting the capacity of the second group by allocating blocks from said first group to said second group in response to a demand to increase the capacity; storing a time stamp with each block, the time stamp having a value that is toggled when the block was programmed; updating a free block list at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data. - View Dependent Claims (8, 9, 10, 11, 12)
- a method of operating the nonvolatile memory, comprising;
Specification