Memory circuit system and method

• US 8,244,971 B2
• Filed: 10/30/2007
• Issued: 08/14/2012
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Campos, Yaima
• Application Number:
  US11/929,636
• Publication Number:
  US 20090024790A1
• Time in Patent Office: 1,750 Days
• Field of Search: 711/105, 711/167, 711170-173, 703/21, 703/28, 365/189.2, 365/194, 365/209
• US Class Current: 711/105
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Claims

1. A memory apparatus, the memory apparatus comprising:

a plurality of physical memory circuits including a first group of physical memory circuits;

an interface circuit operable to interface the plurality of physical memory circuits and a host system, the interface circuit including;

a first component of a first type; and

a second component of a second type, the first and the second components being operable to present, in combination, a simulated memory circuit to a host system, where a first aspect of the simulated memory circuit is different from a corresponding second aspect of each physical memory circuit of the plurality of physical memory circuits, the first aspect and the corresponding second aspect each include at least one of a signal, a memory capacity or a timing,

where each physical memory circuit of the first group of physical memory circuits is electrically coupled to the second component,

where the first component is operable to receive (1) address signals and (2) power management signals other than address signals from the host system and send at least one of the power management signals received from the host system to the second component, and

where the second component is operable to receive a first set of data signals from the host system and send the first set of data signals received from the host system to at least one physical memory circuit of the first group of physical memory circuits.

2. The memory apparatus of claim 1, where the at least one power management signal is associated with a power saving operation.

3. The memory apparatus of claim 2, where the power saving operation includes a power off operation.

4. The memory apparatus of claim 1, where the at least one power management signal is an encoded signal.

5. The memory apparatus of claim 1, where the second component is operable to send the first set of data signals to the at least one physical memory circuit of the first group of physical memory circuits after a delay.

6. The memory apparatus of claim 5, where the delay is a fraction of a clock cycle.

7. The memory apparatus of claim 6, where the delay is one half clock cycle delay.

8. The memory apparatus of claim 1, further comprising a third component of the second type,

where the plurality of physical memory circuits includes a second group of physical memory circuits different from the first group of physical memory circuits, where the first component is operable to send at least one of the power management signals to the third component, and where the third component is operable to receive a second set of data signals from the host system and send the second set of data signals received from the host system to at least one physical memory circuit of the second group of physical memory circuits.

9. The memory apparatus of claim 8, further comprising:

a first buffered stack that includes the first group of physical memory circuits, where the first group of physical memory circuits is coupled to the second component; and

a second buffered stack that includes the second group of physical memory circuits, where the second group of physical memory circuits is coupled to the third component.

10. The memory apparatus of claim 9, further comprising a dual-inline memory module (DIMM), where the DIMM includes the first component, the first buffered stack and the second buffered stack.

11. The memory apparatus of claim 9, where the first component is electrically coupled to the first buffered stack and to the second buffered stack.

12. The memory apparatus of claim 1, where the first type of component is a register and the second type of component is a buffer.

13. The memory apparatus of claim 1, further comprising a dual-inline memory module (DIMM), where the DIMM includes the plurality of physical memory circuits, the plurality of physical memory circuits being coupled to the DIMM.

14. The memory apparatus of claim 13, where the DIMM includes the second component.

15. The memory apparatus of claim 14, where DIMM includes the first component.

16. The memory apparatus of claim 13, where the plurality of physical memory circuits comprises a stack of dynamic random access memory (DRAM) circuits.

17. The memory apparatus of claim 16, where the DIMM comprises a plurality of address, control, and clock buses.

18. The memory apparatus of claim 16, where the DIMM comprises a single shared address, control, and clock bus coupled to each physical memory circuit of the plurality of physical memory circuits in the stack.

19. The memory apparatus of claim 16, where the DIMM comprises a shared data bus coupled to two or more physical memory circuits of the plurality of physical memory circuits.

20. The memory apparatus of claim 16, where the DIMM comprises a plurality of data buses, each data bus of the plurality of data buses being coupled to two or more physical memory circuits of the plurality of physical memory circuits.

21. The memory apparatus of claim 16, where the DIMM comprises a plurality of data buses, each data bus of the plurality of data buses being respectively coupled to a different physical memory circuit of the plurality of physical memory circuits.

22. The memory apparatus of claim 1, where the first aspect of the simulated memory circuit is associated with a first signal relating to a mode register operation and the corresponding second aspect of each physical memory circuit is associated with a different signal relating to the mode register operation.

23. The memory apparatus of claim 1, where the first aspect of the simulated memory circuit includes a first memory capacity and the corresponding second aspect of each physical memory circuit includes a second different capacity.

24. The memory apparatus of claim 1, where the first aspect of the simulated memory circuit includes a first operation latency and the corresponding second aspect of each physical memory circuit includes a second different operation latency.

25. The memory apparatus of claim 1, where the simulated memory circuit includes a first number of simulated banks and the plurality of physical memory circuits includes a second different number of banks.

26. The memory apparatus of claim 1, where the first and the second components are operable to present, in combination, a plurality of simulated memory circuits to the host system, where the first aspect is associated with each simulated memory circuit of the plurality of simulated memory circuits.

27. The memory apparatus of claim 26, where a total number of the physical memory circuits is greater than a total number of the simulated memory circuits.

28. The memory apparatus of claim 1, where at least one of the first or second components is further operable to:

select one or more physical memory circuits of the first group of physical memory circuits by generating one or more chip select signals; and

perform an operation on the one or more selected physical memory circuits.

29. The memory apparatus of claim 1, where the first group includes two or more physical memory circuits.

30. The memory apparatus of claim 1, where at least one of the first or second components is further operable to:

identify one or more physical memory circuits of the first group of physical memory circuits as not being accessed; and

perform a power-saving operation on the one or more physical memory circuits of the first group identified as not being accessed.

31. The memory apparatus of claim 30, where the at least one of the first or second components is operable to perform the power-saving operation by placing at least one physical memory circuit of the one or more physical memory circuits of the first group identified as not being accessed in a precharge power down mode.

32. The memory apparatus of claim 31, where the at least one of the first or second components is operable to place the at least one physical memory circuit of the one or more physical memory circuits of the first group identified as not being accessed in a precharge power down mode by controlling a clock enable input of the at least one physical memory circuit.

33. The memory apparatus of claim 30, where the at least one of the first or second components is operable to identify the one or more physical memory circuits of the first group as not being accessed based on how many pages are open in at least one physical memory circuit of the first group of physical memory circuits.