Error correcting code generation method and memory control apparatus

• US 8,245,110 B2
• Filed: 07/30/2008
• Issued: 08/14/2012
• Est. Priority Date: 01/31/2006
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miura, Takashi
• Primary Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US12/182,732
• Publication Number:
  US 20090031188A1
• Time in Patent Office: 1,476 Days
• Field of Search: None
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

An objective of the present invention is to make it possible to appropriately correct an error of data in a cache memory. A store processing unit generates an nt-ECC on the basis of data stored in a non-target area that was read out from a cache memory with a search of the cache memory, and generates t-ECC on the basis of the data to be stored in the buffer.

Claims

1. An error correcting code generation method, comprising:

storing data to be stored in a store instruction in a buffer;

searching a cache memory to perform a judgment as to whether the data to be stored exists in the cache memory;

when the data to be stored exists in the cache memory according to the judgment, generating a first error correcting code on the basis of data other than the data to be stored that was read out from the cache memory with the search of the cache memory, and keeping the generated first error correcting code;

generating a second error correcting code on the basis of the data to be stored in the buffer; and

generating an error correcting code for the data by merging the first error correcting code and the second error correcting code, wherein

a judgment as to whether a store address in a preceding store instruction corresponds to a store address in a current store instruction, and a judgment as to whether a data width of the data to be stored in the current store instruction corresponds to a predetermined data width are performed, and when the preceding store instruction having a same store address exists and the data width of the data in the current store instruction is smaller than the predetermined data width, ECC validity information showing whether the first error correcting code is appropriate is set as invalid, and the ECC validity information is associated and stored with the data and the first error correcting code.

2. The error correcting code generation method according to claim 1, wherein

the buffer comprises a plurality of buffers and a judgment as to whether a same address exists in the plurality of buffers and a judgment as to whether a data width of the data in the current store instruction corresponds to the predetermined data width are performed, and when the same store address exists in the plurality of the buffers and the data width of the data in the current store instruction is smaller than the predetermined data width, the ECC validity information is set as invalid, and the ECC validity information is associated with the data and the first error correcting code, and stored in the corresponding store address in the buffer.

3. The error correcting code generation method according to claim 1, wherein

a judgment as to whether the ECC validity information is set as valid or invalid is performed, and when the ECC validity information is set as valid, the first error correcting code and the second error correcting code are merged to generate an error correcting code for the data.

4. The error correcting code generation method according to claim 1, wherein

when the preceding store instruction is completed while the ECC validity information in the buffer is set as invalid, the ECC validity information in a corresponding store address in the buffer is changed and to valid.

5. A memory control apparatus comprising:

a buffer that stores data specified by a store instruction;

a judgment circuit that searches a cache memory to judge whether the data to be stored in the store instruction exists in the cache memory;

a first error correcting code generation circuit that generates, when the data to be stored exists in the cache memory according to the judgment performed by the judgment circuit, a first error correcting code on the basis of data other than the data to be stored that was read out from the cache memory with the search of the cache memory and keeping the generated first error correcting code;

a second error correcting code generation circuit that generates a second error correcting code on the basis of the data to be stored in the buffer; and

a merge circuit that generates an error correcting code for the data by merging the first error correcting code and the second error correcting code, wherein

the first error correcting code generation circuit performs a judgment as to whether a store address in a preceding store instruction corresponds to a store address in a current store instruction and a judgment as to whether a data width of the data in the current store instruction corresponds to a predetermined data width, and when a preceding store instruction having a same store address and the data width of the data in the current store instruction is smaller than the predetermined data width, ECC validity information showing whether the first error correcting code is appropriate is set as invalid, and the ECC validity information is associated and stored with the data and the first error correcting code.

6. The memory control apparatus according to claim 5, wherein

the buffer comprises a plurality of buffers;

and

the first error correcting code generation circuit performs a judgment as to whether the same store address exists in the plurality of the buffers and a judgment as to whether a data width of the data in the current store instruction correspond to the predetermined data width, and when the same store address exists in the plurality of the buffers and the data width of the data in the current store instruction is smaller than the predetermined data width, the ECC validity information is set as invalid, and the ECC validity information is associated with the data and the first error correcting code, and stored in the store address in the buffer.

7. The memory control apparatus according to claim 5, wherein

the merge circuit performs a judgment as to whether the ECC validity information is set as valid or invalid, and when the ECC validity information is set as valid, the first error correcting code and the second error correcting code are merged to generate an error correcting code for the data.

8. The memory control apparatus according to claim 5, wherein

when the preceding store instruction is completed while the ECC validity information in the buffer is set as invalid, the ECC validity information in a corresponding store address in the buffer is changed to valid.

9. A non-transitory computer-readable storage medium on which is recorded a program for causing a computer to execute a process generating an error correcting code, said process comprising:

storing data to be stored in a store instruction in a buffer;

searching a cache memory to perform a judgment as to whether the data to be stored exists in the cache memory;

when the data to be stored exists in the cache memory according to the judgment, generating a first error correcting code on the basis of the data other than the data to be stored that was read out from the cache memory with the search of the cache memory, and keeping the generated first error correcting code;

generating a second error correcting code on the basis of the data to be stored in the buffer;

generating an error correcting code for the data by merging the first error correcting code and the second error correcting code;

performing a judgment as to whether a store address in a preceding store instruction corresponds to a store address in a current store instruction, and a judgment as to whether a data width of the data in the current store instruction corresponds to a predetermined data width; and

when the preceding store instruction having a same store address and the data width of the store data in the current store instruction is smaller than the predetermined data width, setting ECC validity information showing whether the first error correcting code is appropriate as invalid, and associating and storing the ECC validity information with the data and the first error correcting code.

10. The non-transitory computer-readable storage medium according to claim 9, wherein

the step of storing the ECC validity information comprises performing a judgment as to whether the same address exists in a plurality of the buffers and whether a data width of the data in the current store instruction correspond to the predetermined data width, and when the same store address exists in the plurality of the buffers and the data width of the data in the current store instruction is smaller than the predetermined data width, setting the ECC validity information as invalid, associating and storing, in the store address in a corresponding buffer, the ECC validity information with the data and the first error correcting code.

11. The non-transitory computer-readable storage medium according to claim 9, wherein

the step of generating the error correcting code comprises performing a judgment as to whether the ECC validity information is set as valid or invalid, and when the ECC validity information is set as valid, merging the first error correcting code and the second error correcting code to generate the error correcting code for the data.

12. The non-transitory computer-readable storage medium according to claim 9, wherein

the step of storing the ECC validity information comprises, when the preceding store instruction is completed while the ECC validity information of the buffer is set as invalid, changing the ECC validity information in the corresponding store address in the buffer to valid.