Wafer level embedded and stacked die power system-in-package packages

• US 8,247,269 B1
• Filed: 06/29/2011
• Issued: 08/21/2012
• Est. Priority Date: 06/29/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Liu, Yong
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/171,577
• Time in Patent Office: 419 Days
• Field of Search: 438/63, 257/E21.5
• US Class Current: 438/107
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/24101 Connecting bonding areas at the same height
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92133 the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Wafer level embedded and stacked die power system-in-package semiconductor devices, and methods for making and using the same, are described. The methods include placing a first side of a substrate frame, which includes through cavity and an adjacent via, on a carrier. A first side of a component selected from an active device and a passive device can be placed on the carrier, within the cavity. A perimeter of the cavity can be attached to a perimeter of the component. Material at a second side of the substrate frame can be removed so the via extends from the frame'"'"'s first side to the frame'"'"'s second side. The substrate frame and component can then be removed from the carrier so that routing can be distributed between the first side of the frame and the first side of the component to electrically connect the component with the via. Other embodiments are described.

Claims

1. A method for making a semiconductor package, comprising:

placing a first side of substrate frame on a carrier, the substrate frame comprising a through cavity that extends from the first side to a second side of the substrate frame and a via that is adjacent to the cavity and that is exposed on the first side of the substrate frame;

placing a first side of a component on the carrier within the cavity of the substrate frame, wherein the component comprises an active device or a passive device;

attaching a perimeter of the cavity of substrate frame to a perimeter of the component;

removing material from the second side of the substrate frame so that the via extends from the first side to the second side of the substrate frame;

removing the substrate frame and the attached component from the carrier; and

placing routing between the first side of the substrate frame and the first side of the component to electrically connect the component with the via.

2. The method of claim 1, wherein the substrate frame comprises glass, silicon, a pre-molded epoxy molding compound, or a combination thereof.

3. The method of claim 1, wherein the substrate frame comprises glass.

4. The method of claim 1, wherein the component comprises an active device.

5. The method of claim 4, further comprising stacking and electrically attaching a first passive component to a portion of the first side of the active device.

6. The method of claim 4, further comprising stacking and electrically attaching multiple passive components to the first side of the active device.

7. The method of claim 4, further comprising applying a bump to the via at the second side of the substrate frame.

8. The method of claim 4, further comprising applying a solder bump to the via at the first side of the substrate frame.

9. The method of claim 1, wherein the component comprises a passive device.

10. The method of claim 9, wherein the passive device comprises an inductor.

11. The method of claim 9, further comprising stacking and electrically connecting an integrated circuit die to the first side of the passive device.

12. The method of claim 9, further comprising applying a bump to the via at the second side of the substrate frame.

13. A method for forming a wafer level embedded package, comprising:

placing a first side of substrate frame on a carrier, wherein the substrate frame comprises a through cavity that extends from the first side to a second side of the substrate frame and a via that is adjacent to the cavity and that is exposed on the first side of the substrate frame;

placing a first side of an active device on the carrier within the cavity of the substrate frame;

attaching a perimeter of the cavity of the substrate frame to a perimeter of the active device;

removing material from the second side of the substrate frame so that the via extends from the first side to the second side of the substrate frame;

removing the substrate frame and the attached active device from the carrier;

placing routing between the first side of the substrate frame and the first side of the active device to electrically connect the active device with the via; and

stacking and electrically attaching a first passive component to the first side of the active device.

14. The method of claim 13, further comprising stacking and electrically attaching an additional passive component to the first side of the active device.

15. The method of claim 13, wherein the substrate frame comprises glass, silicon, an epoxy molding compound, or a combination thereof.

16. The method of claim 13, wherein the substrate frame comprises glass.

17. The method of claim 13, further comprising applying a bump to the via at the second side of the substrate frame.

18. A method for forming a stacked die system-in-package semiconductor device, the method comprising:

placing a first side of substrate frame on a carrier, wherein the substrate frame comprises a through cavity that extends from the first side to the second side of the substrate frame and a via that is adjacent to the cavity and that is exposed on the first side of the substrate frame;

placing a first side of passive device on the carrier within the cavity of the substrate frame;

attaching a perimeter of the cavity of the substrate frame to a perimeter of the passive device;

removing material from the second side of the substrate frame so that the via extends from the first side to the second side of the substrate frame;

removing the substrate frame and the attached passive device from the carrier;

placing routing between the first side of the substrate frame and the first side of the passive device to electrically connect the passive device with the via; and

stacking and electrically connecting an integrated circuit die to the first side of the passive device.

19. The method of claim 18, wherein the passive device comprises an inductor.

20. The method of claim 18, further comprising applying a bump to the via at the first side of the substrate frame.