Method of forming an insulated gate field effect transistor device having a shield electrode structure

• US 8,247,296 B2
• Filed: 12/09/2009
• Issued: 08/21/2012
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M.
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US12/633,967
• Publication Number:
  US 20110136310A1
• Time in Patent Office: 986 Days
• Field of Search: 438/270, 438/454, 438/589, 438/595, 438/700, 438/702, 257/E21.41
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers.

Claims

1. A method of forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface;

forming a dielectric stack overlying the major surface, wherein the dielectric stack comprises a first layer and second layer overlying the first layer, and wherein one layer comprises an oxidation blocking layer;

forming a first opening in the dielectric stack;

forming a trench in the semiconductor substrate through the opening and extending from the major surface;

forming an insulated shield electrode within the trench;

removing the second layer;

forming an insulated gate electrode within the trench, wherein the insulated gate electrode includes a conductive gate material;

removing a portion of the conductive gate material to form a first recessed region above the insulated gate electrode;

forming a dielectric plug within the first recessed region, wherein the dielectric plug comprises a material different than the first layer;

forming a body region in the semiconductor substrate;

removing the first layer;

forming a source region in the body region self-aligned to the dielectric plug;

forming dielectric spacers adjacent the dielectric plug;

forming second recessed regions in the semiconductor substrate self-aligned to the spacers; and

forming a first conductive layer coupled to the semiconductor substrate through the second recessed regions.

2. The method of claim 1, wherein the step of forming the insulated shield electrode comprises the steps of:

forming a first dielectric layer overlying surfaces of the trench, wherein the first dielectric layer has a first thickness;

forming a second dielectric layer overlying the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different materials;

forming a second opening along lower portions of the trench through the first and second dielectric layers;

forming the trench to a second depth greater than the first depth through the second opening to a form shield electrode trench portion;

forming a third dielectric layer along surfaces of the shield electrode trench portion, wherein the third dielectric layer has a second thickness;

forming a shield electrode overlying the third dielectric layer, wherein the shield electrode is recessed within the trench; and

forming a fourth dielectric layer overlying the shield electrodes.

3. The method of claim 2, wherein the step of forming the third dielectric layer includes forming the third dielectric layer, wherein the second thickness is greater than the first thickness.

4. The method of claim 2, wherein the step of forming the first dielectric layer includes forming an oxide layer, and wherein the step of forming the second dielectric comprises forming a nitride layer.

5. The method of claim 2, wherein the step of forming the insulated gate electrode comprises the steps of:

removing portions of the second dielectric layer after the step of forming the fourth dielectric layer; and

forming the gate conductive material overlying the fourth and first dielectric layers.

6. The method of claim 1, wherein the step of forming the first layer includes forming an oxide layer, and wherein the step of forming the second layer includes forming a nitride layer.

7. The method of claim 6, wherein the step of forming the dielectric plug includes forming dielectric plug comprising nitride.

8. The method of claim 7, wherein the step of forming the spacers includes forming oxide spacers.

9. The method of claim 1, further comprising the step of forming a first enhancement region in the first recessed region.

10. The method of claim 9, wherein the step of forming the first enhancement region includes forming a silicide region.

11. The method of claim 1, further comprising the step of forming a second enhancement region in the second recessed region.

12. The method of claim 1, wherein the step of forming the body region includes forming the body region after the step of forming the trench.

13. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface, a pair of adjacent trenches, and a dielectric stack overlying the major surface between the pair of adjacent trenches, wherein the dielectric stack includes at least a first layer and a second layer comprised of different materials;

forming insulated shield electrodes in portions of the pair of adjacent trenches;

removing the second layer;

forming insulated gate electrodes in other portions of the pair of adjacent trenches, wherein the insulated gate electrodes include conductive gate material having a surface in proximity to an upper surface of the first layer;

removing portions of the conductive gate material to form first recessed regions;

forming dielectric plugs in the first recessed regions;

removing at least portions of the first layer;

forming spacers adjacent the dielectric plugs;

removing a portion of the semiconductor substrate self-aligned to the spacers to form a second recessed region;

forming first enhancement regions in the second recessed region; and

forming a conductive layer overlying the dielectric plugs.

14. The method of claim 13 further comprising the steps of:

forming a body region in the semiconductor substrate; and

forming a source region in the body region self-aligned to the dielectric plug.

15. The method of claim 13, wherein the step of providing the semiconductor substrate includes providing a semiconductor substrate wherein the first layer is an oxide and the second layer is a nitride layer, and wherein the step of forming the dielectric plugs includes forming nitride plugs.

16. The method of claim 15 further comprising the step of forming second enhancement regions in the first recessed regions before the step of forming the dielectric plugs.

17. The method of claim 16, wherein the step of forming the second enhancement regions includes forming silicide regions.

18. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface, a pair of adjacent trenches, and a dielectric stack overlying the major surface between the pair of adjacent trenches, wherein the dielectric stack includes at least a first layer and a second layer comprised of different materials;

forming insulated shield electrodes in portions of the pair of adjacent trenches;

removing the second layer;

forming insulated gate electrodes in other portions of the pair of adjacent trenches, wherein the insulated gate electrodes include conductive gate material having a surface in proximity to an upper surface of the first layer;

removing portions of the conductive gate material to form first recessed regions;

forming first enhancement regions in portions of the conductive gate material;

forming dielectric plugs in the first recessed regions;

removing at least portions of the first layer;

forming spacers along sidewalls of the dielectric plugs;

removing a portion of the semiconductor substrate self-aligned to the spacers to form a second recessed region; and

forming a conductive layer coupled to the semiconductor substrate within the second recessed region.

19. The method of claim 18 further comprising the steps of:

forming a body region in the semiconductor substrate; and

forming at least one source region in the body region self-aligned to a dielectric plug.

20. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface;

forming a first trench portion extending from the major surface to a first depth;

forming a gate dielectric layer overlying the first trench portion, wherein the first trench portion and gate dielectric layer have a first lateral dimension, and wherein the step of forming the gate dielectric layer establishes a gate length for the semiconductor device;

forming a first dielectric layer overlying the gate dielectric layer;

forming an opening at the bottom of the first trench portion;

forming a second trench portion through the opening to a second depth greater than the first depth;

forming a second dielectric layer overlying surfaces of the second trench portion, wherein the second trench portion and the second dielectric layer have a second lateral dimension that is greater than the first lateral dimension;

forming a shield electrode overlying the second dielectric layer and recessed within the second trench portion;

forming a third insulating layer overlying the shield electrode;

removing the first dielectric layer; and

forming a gate electrode within the first trench portion, wherein the gate electrode is recessed within the first trench portion.

21. The method of claim 20 further comprising the step of forming a dielectric plug overlying the gate electrode.