Plasma processing apparatus and method for manufacturing semiconductor device

• US 8,247,315 B2
• Filed: 03/10/2009
• Issued: 08/21/2012
• Est. Priority Date: 03/17/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Ichijo, Mitsuhiro, Tajima, Ryota, Yamazaki, Shunpei, Sugiyama, Tetsuo, Nozawa, Taichi
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US12/400,844
• Publication Number:
  US 20090233425A1
• Time in Patent Office: 1,260 Days
• Field of Search: None
• US Class Current: 438/482
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/509 using internal electrodes
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

introducing a first reaction gas into a reaction chamber;

applying a high-frequency power with a frequency of greater than or equal to 30 MHz and less than or equal to 300 MHz to an upper electrode of the reaction chamber to generate glow discharge plasma;

depositing a microcrystalline semiconductor film over a substrate disposed over a lower electrode of the reaction chamber;

introducing a second reaction gas into the reaction chamber;

applying a high-frequency power with a frequency of greater than or equal to 30 MHz and less than or equal to 300 MHz to the upper electrode to generate glow discharge plasma; and

stacking an amorphous semiconductor film over the microcrystalline semiconductor film.

2. A method for manufacturing a semiconductor device, comprising the steps of:

introducing a reaction gas into a reaction chamber;

applying a first high-frequency power with a first frequency of greater than or equal to 3 MHz and less than 30 MHz and a second high-frequency power with a second frequency of greater than or equal to 30 MHz and less than or equal to 300 MHz, which are superposed on each other, to an upper electrode of the reaction chamber to generate glow discharge plasma;

depositing a microcrystalline semiconductor film over a substrate disposed over a lower electrode of the reaction chamber;

introducing hydrogen into the reaction chamber after depositing the microcrystalline semiconductor film; and

applying a third high-frequency power with a third frequency of greater than or equal to 30 MHz and less than or equal to 300 MHz to the upper electrode to perform plasma treatment on the microcrystalline semiconductor film.

3. The method for manufacturing a semiconductor device according to claim 2, wherein a pressure in the reaction chamber before the reaction gas is introduced is in the range of 1×

10<sup>−

8</sup> Pa to 1×

10<sup>−

4</sup> Pa.