Transistor, semiconductor device including the transistor, and manufacturing method of the transistor and the semiconductor device

• US 8,247,812 B2
• Filed: 02/04/2010
• Issued: 08/21/2012
• Est. Priority Date: 02/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Godo, Hiromichi, Shimazu, Takashi
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/699,969
• Publication Number:
  US 20100207117A1
• Time in Patent Office: 929 Days
• Field of Search: 257/43, 257/57, 257/E21.414, 257/E29.068, 257/E29.296, 257/104
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to suppress deterioration in electric characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer, an impurity semiconductor layer is provided over the silicon layer, and a source electrode layer and a drain electrode layer are provided to be electrically connected to the impurity semiconductor layer.

Claims

1. A transistor comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a silicon layer over and in contact with the oxide semiconductor layer;

a first impurity semiconductor layer over the silicon layer;

a second impurity semiconductor layer over the silicon layer;

a source electrode layer electrically connected to the first impurity semiconductor layer; and

a drain electrode layer electrically connected to the second impurity semiconductor layer.

2. The transistor according to claim 1,

wherein the first impurity semiconductor layer and the second impurity semiconductor layer are silicon layers to which an impurity element is added.

3. The transistor according to claim 1,

wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

4. The transistor according to claim 1,

wherein an edge surface of the oxide semiconductor layer is covered with the silicon layer.

5. A semiconductor device comprising the transistor according to claim 1.

6. A transistor comprising;

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a silicon layer over and in contact with the oxide semiconductor layer, the silicon layer including an intrinsic region, a first impurity region, and a second impurity region, wherein the first impurity region and the second impurity region are provided apart from each other with the intrinsic region interposed between the first impurity region and the second impurity region;

a source electrode layer electrically connected to the first impurity region; and

a drain electrode layer electrically connected to the second impurity region.

7. The transistor according to claim 6,

wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

8. The transistor according to claim 6,

wherein an edge surface of the oxide semiconductor layer is covered with the silicon layer.

9. A semiconductor device comprising the transistor according to claim 6.