Two-transistor pixel array

• US 8,247,849 B2
• Filed: 03/15/2012
• Issued: 08/21/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith, Johnson, Kim, Milgrew, Mark
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/421,699
• Publication Number:
  US 20120168784A1
• Time in Patent Office: 159 Days
• Field of Search: 257/253, 257/252
• US Class Current: 257/253
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device.

Claims

1. A device comprising:

an array of pixels, at least some pixels in the array comprising;

a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer; and

a second transistor including a first source/drain terminal, a second source/drain terminal and a gate terminal, wherein the first source/drain terminal of the second transistor is directly connected to the first source/drain terminal of the chemFET; and

a plurality of pairs of lines coupled to pixels in the array, wherein each pair of lines includes a first line directly connected to second source/drain terminals of chemFETs of a corresponding first plurality of pixels in the array, and a second line directly connected to second source/drain terminals of second transistors of the corresponding first plurality of pixels in the array.

2. The device of claim 1, further comprising a plurality of third lines coupled to pixels in the array, wherein each third line is coupled to gate terminals of second transistors of a corresponding second plurality of pixels.

3. The device of claim 2, further comprising circuitry coupled to the third lines and the pairs of lines for reading a selected pixel directly connected to a selected third line and a selected pair of lines, the circuitry comprising:

bias circuitry to apply a bias voltage to one of the first and second lines of the selected pair of lines, and to apply a pass voltage to a third line coupled to the gate terminal of the second transistor of the selected pixel; and

sense circuitry to read the selected pixel based on a sampled voltage level on the other of the first and second lines of the selected pair of lines.

4. The device of claim 3, wherein the bias circuitry includes a current source coupled to said other of the first and second lines of the selected pair to provide a bias current to the selected pixel, and the sampled voltage level on said other of the first and second lines is established based on a threshold voltage of the chemFET of the selected pixel.

5. The device of claim 3, wherein:

the bias circuitry applies the bias voltage to said one of the first and second lines and applies the pass voltage to the gate terminal of the second transistor of the selected pixel during a read interval; and

the sense circuitry includes;

a pre-charge circuit to pre-charge said other of the first and second lines of the selected pair to a pre-charge voltage level prior to the read interval; and

a sample circuit to sample a voltage level on said other of the first and second lines during the read interval.

6. The device of claim 1, wherein channels of the chemFET and the second transistor of pixels in the array have the same conductivity type.

7. The device of claim 1, wherein channels of the chemFET and the second transistor of pixels in the array have different conductivity types.

8. A device comprising:

an array of pixels arranged in a plurality of rows and a plurality of columns, at least some pixels in the array comprising;

a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer; and

a select transistor including a first source/drain terminal, a second source/drain terminal and a control gate terminal, wherein the first source/drain terminal of the select transistor is directly connected to the first source/drain terminal of the chemFET;

a plurality of rows of lines coupled to pixels in the array, wherein a given row line in the plurality of row lines is directly connected to control gate terminals of select transistors of pixels arranged in a corresponding row in the plurality of rows;

a plurality of sets of column lines coupled to pixels in the array, wherein a given set in the plurality of sets is coupled to a pair of adjacent pixels arranged in a given column in the plurality of columns, the given set including a first column line directly connected to the second source/drain terminal of the select transistor of a first pixel of the pair of adjacent pixels, a second column line directly connected to the second source/drain terminal of the select transistor of a second pixel of the pair of adjacent pixels, and a third column line directly connected to the second source/drain terminals of the chemFETs of the pair of adjacent pixels.

9. The device of claim 8, further comprising circuitry for reading the first and second pixels of the pair of adjacent pixels in parallel, the circuitry comprising:

bias circuitry to apply pass voltages to row lines connected to the control gate terminals of select transistors of the first and second pixels of the pair, and to apply a bias voltage to the third column line in the given set; and

sense circuitry to read the first pixel of the pair of adjacent pixels based on a voltage level on the first column line in the given set, and to read the second pixel of the pair of adjacent pixels based on a voltage level on the second column line in the given set.

10. The device of claim 8, wherein channels of the chemFET and the select transistor of each of the pixels in the array have the same conductivity type.

11. The device of claim 10, wherein the channels of the chemFET and the select transistor of each of the pixels in the array are formed in a continuous doped region.

12. The device of claim 8, wherein the second column line of the given pair is directly connected to a second source/drain terminal of a select transistor of another pixel arranged in the given column, and said another pixel is next to the second pixel of the pair of adjacent pixels.

13. A device comprising:

an array of pixels, a given pixel in the array of pixels comprising;

a first chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal, a second source/drain terminal and a floating gate; and

a second chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal, a second source/drain terminal and a floating gate;

a plurality of row lines coupled to the array of pixels, wherein a given row line is directly connected to the first source/drain terminals of first and second chemFETs of the given pixel;

a plurality of pairs of column lines coupled to the array of pixels, wherein a given pair of column lines includes a first line directly connected to the second source/drain terminal of the first chemFET of the given pixel, and a second column line directly connected to the second source/drain terminal of the second chemFET of the given pixel; and

circuitry coupled to the row lines and the pairs of column lines to read the given pixel, the circuitry comprising;

bias circuitry to apply a bias voltage to the given row line; and

sense circuitry to read the given pixel based on a sampled voltage level on the first in the given pair, and further based on a sampled voltage level on the second column line in the given pair.

14. The device of claim 13, wherein the first chemFET of the given pixel has a different sensitivity to a particular analyte than that of the second chemFET of the given pixel, and the sense circuitry reads the given pixel based on a difference between the sampled voltage levels on the first and second column lines.

15. The device of claim 13, wherein the sense circuitry reads the given pixel based on an average of the sampled voltage levels on the first and second column lines.

16. The device of claim 13, wherein the first source/drain terminals of the first and second chemFETs of the given pixel are drain terminals, and the second source/drain terminals of the first and second chemFETs of the given pixel are source terminals.

17. The device of claim 13, wherein the first source/drain terminals of the first and second chemFETs of the given pixel are source terminals, and the second source/drain terminals of the first and second chemFETs of the given pixel are drain terminals.