Semiconductor structure, method for operating a semiconductor structure and method for producing a semiconductor structure

• US 8,247,865 B2
• Filed: 10/05/2006
• Issued: 08/21/2012
• Est. Priority Date: 10/06/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US11/543,732
• Publication Number:
  US 20070108511A1
• Time in Patent Office: 2,147 Days
• Field of Search: 257/339, 257/335, 257/331, 257/332, 257328-330
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor structure has a substrate with a first main surface and a second main surface, the substrate comprising a gate electrode region, a channel region, wherein a conductive channel can be generated, and a gate electrode insulation between the gate electrode region and the channel region.

Further, a field electrode region with a curved external surface is provided for increasing a breakdown voltage of the semiconductor structure, wherein the field electrode region has an extension in every direction in parallel to the first main surface, which is lower than a maximum extension in the one direction perpendicular to the second main surface.

Claims

1. A semiconductor structure comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region comprising a plurality of gate strips;

a channel region, wherein a vertical conductive channel is generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain region;

a field electrode region with a curved external surface for increasing a breakdown voltage of the semiconductor structure, wherein the field electrode region has an extension in every direction in parallel to the first main surface, which is smaller than a maximum extension in a direction perpendicular to the first main surface; and

an electrically insulating layer arranged between the field electrode region and the drain region.

2. The semiconductor structure according to claim 1, wherein the field electrode region has a ratio of a maximum extension in parallel to the first main surface-to a maximum extension perpendicular to the first main surface that lies in a range of 0.05 to 0.5.

3. The semiconductor structure according to claim 1, wherein a maximum extension of the field electrode region in parallel to the first main surface is less than 2 μ

m.

4. The semiconductor structure according to claim 1, wherein the field electrode region has a circular shape, a shape of a regular n-angle or a ring shape in a top view of the first main surface.

5. The semiconductor structure according to claim 1, wherein the field electrode region is fully filled with conductive material within the curved external surface, so that the field electrode region has merely an external surface and no internal surface.

6. The semiconductor structure according to claim 1, wherein a cross section of the field electrode region is reduced in the direction away from the first main surface in parallel to the first main surface.

7. The semiconductor structure according to claim 1, further having a drain-drift region, wherein the field electrode region is electrically insulated from the drain-drift region.

8. The semiconductor structure according to claim 1, further having a source region, wherein the field electrode region is electrically connected to the source region and/or the channel region and/or the gate region.

9. The semiconductor structure according to claim 8, wherein the field electrode region abuts on the channel region and/or the source region.

10. The semiconductor structure according to claim 1, wherein the field electrode region has a plurality of spatially separated field electrode subregions, the centers of which are preferable arranged at grid points of a regular grid.

11. The semiconductor structure according to claim 1, wherein the gate electrode region is arranged in a gate trench.

12. The semiconductor structure according to claim 11, wherein a further field electrode region is arranged in the gate trench.

13. The semiconductor structure according to claim 1, wherein the field electrode region and the gate electrode region are formed contiguously.

14. The semiconductor structure according to claim 1, wherein the gate electrode region and the field electrode region are arranged in a common trench.

15. The semiconductor structure according to claim 1, wherein the gate electrode region is formed strip-shaped in a top view on the first main surface.

16. The semiconductor structure according to claim 15, wherein the gate electrode region has a grid-shaped structure in a top view on the first main surface, which is preferable a square grid structure or a hexagonal grid structure.

17. The semiconductor structure according to claim 1, wherein the gate electrode region splits late a first gate electrode subregion and a second gate electrode subregion, wherein the field electrode region is fully enclosed by the first and second gate electrode subregions in a top view on the first main surface.

18. The semiconductor structure according to claim 1, wherein the semiconductor structure is arranged in a cell and the gate electrode region is arranged in a gate trench, wherein a ratio of p/w_T is in a ranged of 1.2 to 1.6, wherein w_T is the gate trench width and p the cell pitch.

19. A semiconductor structure, comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region comprising a plurality of spatially spaced gate electrode subregions in the form of gate strips;

a channel region, wherein a vertical conductive channel is generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain region;

a spatially closed needle-shaped field electrode region with a curved external surface, which extends in a region having no gate electrode regions between the plurality of spatially spaced gate electrode regions; and

an electrically insulating layer arranged between the field electrode region and the drain region.

20. The semiconductor structure according to claim 19, wherein the field electrode region has a center in top view on the first main surface, which is arranged at a center of the region having no gate electrode regions.

21. The semiconductor structure according to claim 19, wherein the field electrode region has a circular shape, a shape of a regular n-angle or a ring shape in a top view on the first main surface.

22. The semiconductor structure according to claim 19, wherein the field electrode region is fully filled with conductive material within the curved external surface, so that the field electrode region has merely an external surface and no internal surface.

23. The semiconductor structure according to claim 19, wherein a cross section of the field electrode region is reduced in the direction away from the first main surface in parallel to the first main surface.

24. The semiconductor structure according to claim 19, further having a drain-drift region, wherein the field electrode region is electrically insulated from the drain-drift region.

25. The semiconductor structure according to claim 19, further having a source region, wherein the field electrode region is electrically connected to the source region and/or the channel region and/or the gate region.

26. The semiconductor structure according to claim 25, wherein the field electrode region abuts on the channel region and/or the source region.

27. The semiconductor structure according to claim 19, wherein the field electrode region has a plurality of spatially separated field electrode subregions, the centers of which are preferable arranged at grid points of a regular grid.

28. The semiconductor structure according to claim 19, wherein the gate electrode region is arranged in a gate trench.

29. The semiconductor structure according to claim 28, wherein a further field electrode region is arranged in the gate trench.

30. The semiconductor structure according to claim 19, wherein the field electrode region and the gate electrode region are formed contiguously.

31. The semiconductor structure according to claim 19, wherein the gate electrode region and the field electrode region are arranged in a common trench.

32. The semiconductor structure according to claim 19, wherein the gate electrode region is formed strip-shaped in a top view on the first main surface.

33. The semiconductor structure according to claim 32, wherein the gate electrode region has a grid-shaped structure in a top view on the first main surface, which is preferably a square grid structure or a hexagonal grid structure.

34. The semiconductor structure according to claim 19, wherein the gate electrode region splits into a first gate electrode subregion and a second gate electrode subregion, wherein the field electrode region is fully enclosed by the first and second gate electrode subregions in a top view on the first main surface.

35. The semiconductor structure according to claim 19, wherein the semiconductor structure is arranged in a cell and the gate electrode region is arranged in a gate trench, wherein a ration of p/w_T is in a range of 1.2 to 1.6, wherein w_T is the gate trench width and p the cell pitch.

36. A semiconductor structure, comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region wherein the gate electrode region has an elongated strip portion;

a channel region, wherein a vertical conductive channel is generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain region; and

a field electrode region with a curved external surface, wherein the field electrode region is arranged such that an electric effective field for increasing a breakdown voltage of the semiconductor structure can be generated across the curved external surface, which is at least partly parallel to the elongated strip portion; and

wherein the external surface of the field electrode region comprises a circular form in a projection on one of the main surfaces of the substrate.

37. The semiconductor structure according to claim 36, wherein the field electrode region has a circular shape, a shape of a regular n-angle or a ring shape in a top view on the first main surface.

38. The semiconductor structure according to claim 36, wherein the field electrode region is fully filled with conductive material within the curved external surface, so that the field electrode region has merely an external surface and no internal surface.

39. The semiconductor structure according to claim 36, wherein a cross section of the field electrode region is reduced in the direction away from the first main surface in parallel to the first main surface.

40. The semiconductor structure according to claim 36, further having a drain-drift region, wherein the field electrode region is electrically insulated from the drain-drift region.

41. The semiconductor structure according to claim 36, further having a source region, wherein the field electrode region is electrically connected to the source region and/or the channel region and/or the gate region.

42. The semiconductor structure according to claim 41, wherein the field electrode region abuts on the channel region and/or the source region.

43. The semiconductor structure according to claim 36, wherein the field electrode region has a plurality of spatially separated field electrode subregions, the centers of which are preferable arranged at grid points of a regular grid.

44. The semiconductor structure according to claim 36, wherein the gate electrode region is arranged in a gate trench.

45. The semiconductor structure according to claim 44, wherein a further field electrode region is arranged in the gate trench.

46. The semiconductor structure according to claim 36, wherein the field electrode region and the gate electrode region are formed contiguously.

47. The semiconductor structure according to claim 36, wherein the gate electrode region and the field electrode region are arranged in a common trench.

48. The semiconductor structure according to claim 36, wherein the gate electrode region is formed strip-shaped in a top view on the first main surface.

49. The semiconductor structure according to claim 48, wherein the gate electrode region has a grid-shaped structure in a top view on the first main surface, which is preferably a square grid structure or a hexagonal grid structure.

50. The semiconductor structure according to claim 36, wherein the gate electrode region splits into a first gate electrode subregion and a second gate electrode subregion, wherein the field electrode region is fully enclosed by the first and second gate electrode subregions in a top view on the first main surface.

51. The semiconductor structure according to claim 36, wherein the semiconductor structure is arranged in a cell and the gate electrode region is arranged in a gate trench, wherein a ratio of p/w_T is in a ranged of 1.2 to 1.6, wherein the w_T is the gate trench width and p the cell pitch.

52. A method for operating a semiconductor structure, comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region comprising a plurality of gate strips;

a channel region, wherein a vertical conductive channel can be generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain region;

a field electrode region with a curved external surface for increasing a breakdown voltage of the semiconductor structure, wherein the electrode region has an extension in every direction in parallel to the first main surface, which is smaller than a maximum extension in a direction perpendicular to the first main surface;

an electrically insulating layer arranged between the field electrode region and the drain region;

comprising the step of;

applying a voltage to the field electrode region, whereby a lateral electric field is generated, which increases the breakdown voltage of the semiconductor structure.

53. The method according to claim 52, wherein the semiconductor structure has a drain-drift region, wherein in the step of applying a voltage the drain-drift region is fully depleted of free charge carriers by the voltage applied to the field electrode region.

54. A method for producing a semiconductor structure, comprising the steps of:

providing a substrate with a first main surface and a second main surface;

generating a gate electrode region comprising a plurality of gate strips in the substrate;

generating a channel region, wherein a vertical conductive channel is generated in the direction from the first main surface to the second main surface;

generating a field electrode region with a curved external surface for increasing a breakdown voltage of the semiconductor structure, wherein the field electrode region has an extension in every direction in parallel to the first main surface, which is smaller than a maximum extension in the direction perpendicular to the first main surface.

55. The method according to claim 54, further comprising the steps of:

generating a gate trench;

generating the gate electrode region in the gate trench.

56. The method according the claim 54, further comprising the steps of:

generating a field electrode trench in the substrate; and

generating the field electrode region in the field electrode trench.

57. The method according to claim 56, wherein a gate electrode trench is generated simultaneously with the field electrode trench.

58. The method according to claim 54, further comprising the step of generating a full-area metallization on the first main surface.

59. The method according to claim 54, further comprising the step of:

generating an insulating layer on the first main surface;

generating contact vias in the insulating layer;

filling the contact vias with electrically conductive material.

60. A method for operating a semiconductor structure, comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region comprising a plurality of spatially spaced gate electrode subregions in the form of gate strips;

a channel region, wherein a vertical conductive channel can be generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain portion;

a spatially closed needle-shaped field electrode region with a curved external surface, which extends in a region having no gate electrode regions between the plurality of spatially spaced gate electrode regions; and

an electrically insulating layer arranged between the field electrode region and the drain region;

comprising the step of;

applying a voltage to the field electrode region, whereby a lateral electric field is generated, which increases the breakdown voltage of the semiconductor structure.

61. A method for operating a semiconductor structure, comprising:

a substrate with a first main surface and a second main surface;

a gate electrode region;

wherein the gate electrode region has an elongated strip portion;

a channel region, wherein a vertical conductive channel can be generated in the direction from the first main surface to the second main surface;

a gate electrode insulation between the gate electrode region and the channel region;

a drain region; and

a field electrode region with a curved external surface, wherein the field electrode region is arranged such that an electric effective field for increasing a breakdown voltage of the semiconductor structure can be generated across the curved external surface, which is at least partly parallel to the elongated strip portion; and

wherein the external surface of the field electrode region comprises a circular form in a projection on one of the main surfaces of the substrate;

comprising the step of;

applying a voltage to the field electrode region, whereby a lateral electric field is generated, which increases the breakdown voltage of the semiconductor structure.