Supplying power to integrated circuits using a grid matrix formed of through-silicon vias

• US 8,247,906 B2
• Filed: 04/28/2010
• Issued: 08/21/2012
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H., Yeh, Wei-Chih
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US12/769,334
• Publication Number:
  US 20110001249A1
• Time in Patent Office: 846 Days
• Field of Search: 257/774, 257/776, 257/E23.067
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses

Abstract

An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Claims

1. An integrated circuit structure comprising:

a chip comprising a substrate; and

a power distribution network comprising;

a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid, and wherein the plurality of power TSVs comprises;

a plurality of VDD TSVs electrically interconnected to each other; and

a plurality of VSS TSVs electrically interconnected to each other and disconnected from the plurality of VDD TSVs, wherein the plurality of VDD TSVs and the plurality of VSS TSVs are allocated in an alternating pattern; and

a plurality of metal lines, wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

2. The integrated circuit structure of claim 1, wherein the plurality of power TSVs is distributed substantially uniformly throughout an entirety of the substrate.

3. The integrated circuit structure of claim 1, wherein throughout the chip, local power routing from the plurality of power TSVs to respective surrounding integrated circuit devices is substantially in a bottom metal layer (M1) and an immediate overlying layer (M2), and is not in metal layers over the M2.

4. The integrated circuit structure of claim 1, wherein the plurality of VDD TSVs is aligned along first parallel lines parallel to an edge of the chip with no VSS TSV in the first parallel lines, and the plurality of VSS TSVs is aligned along second parallel lines parallel to an edge of the chip with no VDD TSV in the second parallel lines.

5. The integrated circuit structure of claim 1, wherein the plurality of VDD TSVs is aligned along first parallel lines parallel to a diagonal direction of the chip with no VSS TSV in the first parallel lines, and the plurality of VSS TSVs is aligned along second parallel lines parallel to the first parallel lines with no VDD TSV in the second parallel lines.

6. The integrated circuit structure of claim 1, wherein the chip comprises a plurality metallization layers, and wherein substantially none of the plurality of power TSVs are electrically coupled to metal features in a top metallization layer among the plurality of the metallization layers.

7. The integrated circuit structure of claim 6, wherein electrical connections to the plurality of power TSVs are substantially limited in the M1 and a metallization layer (M2) immediately over the M1.

8. The integrated circuit structure of claim 1 further comprising:

a first plurality of redistribution lines (RDLs) on a backside of the chip, wherein each of the first plurality of RDLs electrically couples a portion of the plurality of VDD TSVs;

a first bump coupled to each of the first plurality of RDLs;

a second plurality of RDLs on the backside of the chip, wherein each of the second plurality of RDLs electrically couples a portion of the plurality of VSS TSVs; and

a second bump coupled to each of the second plurality of RDLs.

9. The integrated circuit structure of claim 1, wherein the chip comprise a plurality of sub regions each corresponding to one of functional blocks, and wherein the plurality of power TSVs comprises a portion in each of the functional blocks.

10. The integrated circuit structure of claim 9, wherein a portion of the power TSVs is located on boundaries of the sub regions.

11. The integrated circuit structure of claim 9, wherein the sub regions comprise a first sub region and a second sub region having a boundary, wherein the plurality of power TSVs comprises a first portion in the first sub region and close to the boundary, and a second portion in the second sub region and close to the boundary, and wherein none of the plurality power TSVs are located on the boundary.

12. The integrated circuit structure of claim 9, wherein the plurality of sub regions comprises a macro region, wherein the integrated circuit structure further comprises an additional plurality of power TSVs close to the macro region, and wherein the additional plurality of power TSVs comprises and additional plurality of VDD TSVs and an additional plurality of VSS TSVs.

13. The integrated circuit structure of claim 12, wherein the additional plurality of VDD TSVs forms a zigzag pattern, and the additional plurality of VSS TSVs forms a zigzag pattern.

14. The integrated circuit structure of claim 12, wherein no power TSV is formed in the macro region, wherein the integrated circuit structure further comprises metal connections in a third metallization layer (M3) two layers above the M1, and wherein the metal connections connect the additional plurality of power TSVs to circuits in the macro region.

15. The integrated circuit structure of claim 12, wherein the additional plurality of VDD TSVs and the additional plurality of VSS TSVs are off-grid TSVs.

16. An integrated circuit structure comprising:

a chip comprising a semiconductor substrate;

a first plurality of VDD through-silicon vias (TSVs) penetrating the semiconductor substrate;

a first plurality of VSS TSVs penetrating the semiconductor substrate, wherein the first plurality of VDD TSVs and the first plurality of VSS TSVs form a first grid, and are allocated in a substantially alternating pattern in each row and each column of the first grid;

a transistor on a front side of the semiconductor substrate;

a first plurality of redistribution lines (RDLs) on a backside of the semiconductor substrate opposite the front side, wherein each of the first plurality of RDLs electrically couples a portion of the first plurality of VDD TSVs; and

a second plurality of RDLs on the backside of the semiconductor substrate, wherein each of the second plurality of RDLs electrically couples a portion of the first plurality of VSS TSVs.

17. The integrated circuit structure of claim 16, wherein the first grid is distributed in a first portion of the semiconductor substrate, wherein the integrated circuit structure further comprises a second grid formed of a second plurality of VDD TSVs and a second plurality of VSS TSVs and distributed in a second portion of the semiconductor substrate, and wherein the first grid and the second grid have different grid sizes.

18. The integrated circuit structure of claim 16 further comprising a first plurality of metal lines in a bottom metallization layer (M1), wherein the first plurality of metal lines couples the first plurality of VDD TSVs and the first plurality of VSS TSVs to integrated circuit devices on the semiconductor substrate.

19. The integrated circuit structure of claim 16, wherein electrical connections to the first plurality of VDD TSVs are substantially limited in the M1 and a metallization layer (M2) directly over the M1, and wherein substantially none of the first plurality of VDD TSVs are electrically coupled to metal features in any metallization layer over the M2.

20. The integrated circuit structure of claim 16, wherein the first grid forms a voltage island, with the first plurality of VDD TSVs carrying a first voltage, and wherein the integrated circuit structure further comprises an additional grid comprising a second plurality of VDD TSVs carrying a second voltage different from the first voltage.