Configurable IC'S with large carry chains

• US 8,248,102 B2
• Filed: 05/17/2010
• Issued: 08/21/2012
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Redgrave, Jason, Schmit, Herman, Hutchings, Brad L., Huang, Randy R.
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/781,789
• Publication Number:
  US 20110031998A1
• Time in Patent Office: 827 Days
• Field of Search: 326 37- 41, 326/47, 708/230, 708/232, 708/710
• US Class Current: 326/38
• CPC Class Codes: G06F 2207/3868 Bypass control, i.e. possibility to transfer an operand unchanged to the output
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Claims

1. An integrated circuit (IC) comprising:

a plurality of configuration data storage elements for storing a plurality of configuration data sets; and

a region comprising;

an arrangement of configurable logic circuits of a particular type having a plurality of rows and a plurality of columns,

wherein each configurable logic circuit is for performing one of a plurality of operations based on one of the plurality of configuration data sets,

wherein at least one of the plurality of operations is a mathematical operation that produces propagate and generate signals for performing a larger mathematical operation; and

a direct connection connecting first and second configurable logic circuits in said arrangement in order to enable the first and second configurable logic circuits to perform the larger mathematical operation, wherein the first configurable logic circuit and the second configurable logic circuit are not vertically or horizontally aligned and are separated by at least three rows and at least one column or at least three columns and at least one row of configurable logic circuits of the particular type, the direct connection comprising a plurality of wire segments and a plurality of intervening buffer circuits along the plurality of wire segments for relaying a signal from the first configurable logic circuit to the second configurable logic circuit.

2. The IC of claim 1, wherein the second configurable logic circuit comprises a third configurable logic circuit and a set of input select interconnect circuits that supply inputs to the third configurable logic circuit.

3. The IC of claim 1, wherein the direct connection does not include an intervening configurable routing circuit.

4. The IC of claim 1 further comprising a plurality of carry circuits, wherein the direct connection is for providing a carry signal from a first carry circuit to a second carry circuit, wherein the first carry circuit is shared by a first set of configurable logic circuits, wherein the second carry circuit is shared by a second set of configurable logic circuits.

5. The IC of claim 4, wherein the first set of configurable logic circuits comprises four configurable logic circuits, wherein each of the four configurable logic circuits is adjacent to the other three configurable logic circuits in the first set of configurable logic circuits.

6. The IC of claim 4, wherein each configurable logic circuit in the first set of configurable logic circuits produces a generate signal and a propagate signal for the first carry circuit.

7. The IC of claim 6, wherein each configurable logic circuit of the particular type comprises look up tables (LUTs) for producing the generate signal and the propagate signal.

8. The IC of claim 6, wherein the first carry circuit receives propagate and generate signals only from the first set of configurable logic circuits.

9. The IC of claim 1, wherein the region further comprises another direct connection between the second configurable logic circuit and a third configurable logic circuit in said arrangement, wherein the second configurable logic circuit and the third configurable logic circuit are not vertically or horizontally aligned.

10. The IC of claim 9, wherein the direct connections are for performing an expanded arithmetic operation using at least three sets of configurable logic circuits and shared carry circuits.

11. An electronic device comprising:

an electronic memory for storing a plurality of configuration data sets; and

an integrated circuit (IC) comprising;

a region comprising;

an arrangement of configurable logic circuits of a particular type having N columns and M rows,

wherein N and M are integer values that are greater than 10,

wherein each configurable logic circuit is for performing one of a plurality of operations based on one of the plurality of configuration data sets,

wherein at least one of the plurality of operations is a mathematical operation that produces propagate and generate signals for performing a larger mathematical operation; and

a direct connection connecting first and second configurable logic circuits in said arrangement in order to enable the first and second configurable logic circuits to perform the larger mathematical operation, wherein the first configurable logic circuit and the second configurable logic circuit are not vertically or horizontally aligned and are separated by at least one row and at least one column of configurable logic circuits of the particular type, the direct connection comprising a plurality of wire segments and a plurality of intervening buffer circuits for relaying a signal from the first configurable logic circuit to the second configurable logic circuit.

12. The electronic device of claim 11, wherein the second configurable logic circuit comprises a third configurable logic circuit and a set of input select interconnect circuits that supply inputs to the third configurable logic circuit.

13. The electronic device of claim 11, wherein the direct connection does not include an intervening configurable routing circuit.

14. The electronic device of claim 11, wherein the IC further comprises a plurality of carry circuits, wherein the direct connection is for providing a carry signal from a first carry circuit to a second carry circuit, wherein the first carry circuit is shared by a first set of configurable logic circuits, wherein the second carry circuit is shared by a second set of configurable logic circuits.

15. The electronic device of claim 14, wherein the first set of configurable logic circuits comprises four configurable logic circuits, wherein each of the four configurable logic circuits is adjacent to the other three configurable logic circuits in the first set of configurable logic circuits.

16. The electronic device of claim 14, wherein each configurable logic circuit in the first set of configurable logic circuits produces a generate signal and a propagate signal for the first carry circuit.

17. The electronic device of claim 11, wherein the first and second configurable logic circuits are separated by at least three columns or at least three rows of configurable logic circuits of the particular type.

18. An integrated circuit (IC) comprising:

a plurality of configuration data storages for storing configuration data;

a plurality of sets of configurable logic circuits for configurably performing a plurality of operations based on said configuration data, wherein at least one of the plurality of operations comprises an expanded arithmetic operation that is performed by at least two sets of configurable logic circuits;

a plurality of direct connections for allowing the two sets of configurable logic circuits to perform said expanded arithmetic operation, each direct connection connecting two configurable logic circuits that (i) are not vertically or horizontally aligned and (ii) are separated by at least one row and at least one column of configurable logic circuits, at least one of the direct connections comprising a plurality of wire segments and a plurality of buffer circuits along the wire segments for relaying a signal from a first configurable logic circuit to a second configurable logic circuit.

19. The IC of claim 18, wherein at least one direct connection is for performing the expanded arithmetic operation by providing a carry signal from a first set of configurable logic circuits to a second set of configurable logic circuits.

20. The IC of claim 18, wherein the first and second configurable logic circuits are separated by at least three columns or at least three rows of configurable logic circuits.