Successive approximation register (SAR) analog-to-digital converter (ADC) having optimized filter
First Claim
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1. An apparatus comprising:
- a comparator to compare an analog input voltage signal received at a first input with a feedback signal received at a second input;
a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparator output;
a delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate a one-bit decision; and
a digital-to-analog converter (DAC) coupled to the DSM to convert the one-bit decision to the feedback signal, and including an inverter and a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator.
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Abstract
A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
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Citations
18 Claims
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1. An apparatus comprising:
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a comparator to compare an analog input voltage signal received at a first input with a feedback signal received at a second input; a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparator output; a delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate a one-bit decision; and a digital-to-analog converter (DAC) coupled to the DSM to convert the one-bit decision to the feedback signal, and including an inverter and a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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comparing an analog voltage signal received at a first input with a feedback signal received at a second input; updating a bit of a N-bit successive approximation register (SAR) based on the comparison; receiving an N-bit output of the SAR and generating a one-bit decision in a delta-sigma modulator (DSM); converting the one-bit decision to an analog signal in a digital-to-analog converter (DAC); and filtering the analog signal to provide the feedback signal for the comparison. - View Dependent Claims (10, 11, 12, 13)
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14. A system comprising:
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a mechanically tuned radio having a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal; an auxiliary ADC to receive a selected analog signal from a multiplexer and to convert the selected analog signal to a digitized code, the auxiliary ADC including; a comparator having a first input to receive the selected analog signal and a second input to receive a feedback signal and to output a comparison signal; a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparison signal; a one-bit delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate a one-bit decision; a digital-to-analog converter (DAC) coupled to the one-bit DSM to convert the one-bit decision to an analog feedback signal; and a low pass filter (LPF) coupled to the DAC to filter the analog feedback signal and to output the feedback signal to the second input of the comparator, wherein the LPF is at least a fourth-order filter; and a reference voltage generator to receive a battery voltage and generate an attenuated battery voltage therefrom, the reference voltage generator further including a selector to receive the attenuated battery voltage, a bandgap voltage, and a third reference voltage and to dynamically select one of the attenuated battery voltage, the bandgap voltage and the third reference voltage to provide as a reference voltage to the DAC. - View Dependent Claims (15, 16, 17, 18)
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Specification