Successive approximation register (SAR) analog-to-digital converter (ADC) having optimized filter

• US 8,248,280 B2
• Filed: 09/29/2009
• Issued: 08/21/2012
• Est. Priority Date: 09/29/2009
• Status: Expired due to Fees

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Zhan, Sanyi, Cooley, Daniel J., Zhang, Ligang
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US12/568,811
• Publication Number:
  US 20110075768A1
• Time in Patent Office: 1,057 Days
• Field of Search: 341118-121, 341/143, 341/155, 341/172
• US Class Current: 341/118
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 3/506 the final digital/analogue converter being constituted by a pulse width modulator

Abstract

A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.

Claims

1. An apparatus comprising:

a comparator to compare an analog input voltage signal received at a first input with a feedback signal received at a second input;

a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparator output;

a delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate a one-bit decision; and

a digital-to-analog converter (DAC) coupled to the DSM to convert the one-bit decision to the feedback signal, and including an inverter and a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator.

2. The apparatus of claim 1, wherein the LPF comprises a fourth-order LPF.

3. The apparatus of claim 2, wherein N is greater than 10 bits.

4. The apparatus of claim 1, further comprising a multiplexer to receive a plurality of analog signals and select one of the plurality of analog signals to provide to the comparator.

5. The apparatus of claim 4, further comprising a sample and hold circuit coupled to receive the selected analog signal from the multiplexer and to pass a pulse corresponding to the analog input voltage signal that does not vary until the SAR generates a final result.

6. The apparatus of claim 1, wherein the DAC is coupled to receive a reference voltage coherent with a battery voltage.

7. The apparatus of claim 1, further comprising a reference voltage generator to receive a battery voltage and to provide an attenuated battery voltage to a selector.

8. The apparatus of claim 7, wherein the selector is further coupled to receive a bandgap voltage and a third reference voltage and to dynamically select one of the attenuated battery voltage, the bandgap voltage or the third reference voltage to provide as a reference voltage to the DAC.

9. A method comprising:

comparing an analog voltage signal received at a first input with a feedback signal received at a second input;

updating a bit of a N-bit successive approximation register (SAR) based on the comparison;

receiving an N-bit output of the SAR and generating a one-bit decision in a delta-sigma modulator (DSM);

converting the one-bit decision to an analog signal in a digital-to-analog converter (DAC); and

filtering the analog signal to provide the feedback signal for the comparison.

10. The method of claim 9, further comprising filtering the analog signal using a fourth-order low pass filter (LPF).

11. The method of claim 9, further comprising operating the DAC using a reference voltage coherent with a battery voltage.

12. The method of claim 9, further comprising receiving a selected analog signal from a multiplexer coupled to receive a plurality of analog signals and passing a pulse corresponding to the selected analog signal that does not vary until the SAR generates a final result, wherein the plurality of analog signals includes a plurality of sensor outputs and an output of a potentiometer coupled to a battery voltage and user controllable to select a tuning frequency for a desired radio channel, wherein the potentiometer output is indicative of the tuning frequency.

13. The method of claim 12, further comprising providing a reference voltage coherent with the battery voltage to the DAC when the potentiometer output is the selected analog signal.

14. A system comprising:

a mechanically tuned radio having a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal;

an auxiliary ADC to receive a selected analog signal from a multiplexer and to convert the selected analog signal to a digitized code, the auxiliary ADC including;

a comparator having a first input to receive the selected analog signal and a second input to receive a feedback signal and to output a comparison signal;

a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparison signal;

a one-bit delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate a one-bit decision;

a digital-to-analog converter (DAC) coupled to the one-bit DSM to convert the one-bit decision to an analog feedback signal; and

a low pass filter (LPF) coupled to the DAC to filter the analog feedback signal and to output the feedback signal to the second input of the comparator, wherein the LPF is at least a fourth-order filter; and

a reference voltage generator to receive a battery voltage and generate an attenuated battery voltage therefrom, the reference voltage generator further including a selector to receive the attenuated battery voltage, a bandgap voltage, and a third reference voltage and to dynamically select one of the attenuated battery voltage, the bandgap voltage and the third reference voltage to provide as a reference voltage to the DAC.

15. The system of claim 14, further comprising a potentiometer coupled to the battery voltage and user controllable to select a tuning frequency.

16. The system of claim 15, wherein the auxiliary ADC is coupled to receive an output of the potentiometer as the selected analog signal and to output the digitized code corresponding to the tuning frequency.

17. The system of claim 16, further comprising a microcontroller unit (MCU) coupled to the auxiliary ADC to receive the digitized code and to control at least one analog front end (AFE) component of the mechanically tuned radio based thereon.

18. The system of claim 16, wherein the reference voltage generator is to provide the attenuated battery voltage as the reference voltage to the DAC when the auxiliary ADC is coupled to receive the potentiometer output.