Track and hold architecture with tunable bandwidth

• US 8,248,282 B2
• Filed: 08/17/2010
• Issued: 08/21/2012
• Est. Priority Date: 08/17/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Payne, Robert F., Corsi, Marco
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/857,674
• Publication Number:
  US 20120044004A1
• Time in Patent Office: 735 Days
• Field of Search: 341/155, 341/122, 341/123, 327/390, 327/93, 327/97, 327/589, 327/288
• US Class Current: 341/123
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/1215 using time-division multiplexing

Abstract

To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

Claims

1. An apparatus comprising:

a clock divider that receives a clock signal;

a plurality analog-to-digital converter (ADC) branches that each receive an analog input signal, wherein each ADC branch includes;

a delay circuit that is coupled to the clock divider;

an ADC having;

a bootstrap circuit that is coupled to the delay circuit;

a sampling switch that is coupled to the bootstrap circuit; and

a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated;

a sampling capacitor that is coupled to the sampling switch; and

an correction circuit that is coupled to the ADC; and

a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches.

2. The apparatus of claim 1, wherein the apparatus further comprises a multiplexer that is coupled to each ADC branch.

3. The apparatus of claim 2, wherein the correction circuit adjusts the output of its ADC to correct for DC offset and gain mismatch.

4. The apparatus of claim 2, wherein the bootstrap circuit further comprises:

a boost capacitor that is charged during a hold phase of the ADC;

a transistor having first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the transistor is coupled to the boost capacitor, and wherein the second passive electrode of the transistor is coupled to the sampling switch;

a passgate circuit that is coupled to the delay circuit, that is coupled to the control electrode of the transistor, and that receives the control voltage; and

a skew circuit that is coupled to sampling switch and that is controlled by the control voltage.

5. The apparatus of claim 4, wherein the transistor further comprises a first transistor, and wherein the passgate circuit further comprises:

a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to the controller so as to receive the control voltage, and wherein the control electrode of the second transistor is coupled to the delay circuit, and wherein the second passive electrode of the second transistor is coupled to the control electrode of the first transistor;

a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to the second passive electrode of second transistor, and wherein the control electrode of the third transistor is coupled to the delay circuit; and

a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the control electrode of the first transistor, and wherein the control electrode of the fourth transistor is coupled to the sampling switch, and wherein the second passive electrode of the fourth transistor is coupled to the second passive electrode of the third transistor.

6. The apparatus of claim 5, wherein the skew circuit further comprises a fifth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fifth transistor is coupled to the sampling switch, and wherein the control electrode of the fifth transistor is coupled to the controller so as to receive the control voltage.

7. The apparatus of claim 6, wherein the controller is a digital-to-analog converter (DAC).

8. The apparatus of claim 6, wherein the controller is a charge pump.

9. An apparatus comprising:

a clock divider that receives a clock signal;

a plurality ADC branches that each receive an analog input signal, wherein each ADC branch includes;

a delay circuit that is coupled to the clock divider;

an ADC having;

a bootstrap circuit that is coupled to the delay circuit;

a sampling switch that is coupled to the bootstrap circuit;

a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated;

a sampling capacitor that is coupled to the sampling switch;

an output circuit that is coupled to the sampling capacitor; and

a sub-ADC that is coupled to the output circuit; and

an correction circuit that is coupled to the ADC;

a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches; and

a multiplexer that is coupled to each ADC branch.

10. The apparatus of claim 9, wherein the correction circuit adjusts the output of its ADC to correct for DC offset and gain mismatch.

11. The apparatus of claim 9, wherein the bootstrap circuit further comprises:

a boost capacitor that is charged during a hold phase of the ADC;

a transistor having first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the transistor is coupled to the boost capacitor, and wherein the second passive electrode of the transistor is coupled to the sampling switch;

a passgate circuit that is coupled to the delay circuit, that is coupled to the control electrode of the transistor, and that receives the control voltage; and

a skew circuit that is coupled to sampling switch and that is controlled by the control voltage.

12. The apparatus of claim 11, wherein the transistor further comprises a first transistor, and wherein the passgate circuit further comprises:

a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to the controller so as to receive the control voltage, and wherein the control electrode of the second transistor is coupled to the delay circuit, and wherein the second passive electrode of the second transistor is coupled to the control electrode of the first transistor;

a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to the second passive electrode of second transistor, and wherein the control electrode of the third transistor is coupled to the delay circuit; and

a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the control electrode of the first transistor, and wherein the control electrode of the fourth transistor is coupled to the sampling switch, and wherein the second passive electrode of the fourth transistor is coupled to the second passive electrode of the third transistor.

13. The apparatus of claim 12, wherein the skew circuit further comprises a fifth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fifth transistor is coupled to the sampling switch, and wherein the control electrode of the fifth transistor is coupled to the controller so as to receive the control voltage.

14. The apparatus of claim 13, wherein the controller is a DAC.

15. The apparatus of claim 13, wherein the controller is a charge pump.

16. An apparatus comprising:

a clock divider that receives a clock signal;

a plurality ADC branches that each receive an analog input signal, wherein each ADC branch includes;

a delay circuit that is coupled to the clock divider;

an ADC having;

a bootstrap circuit that is coupled to the delay circuit;

a PMOS transistor that is coupled to the bootstrap circuit;

a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated;

a sampling capacitor that is coupled to the PMOS transistor at its drain;

an output circuit that is coupled to the sampling capacitor; and

a sub-ADC that is coupled to the output circuit; and

an correction circuit that is coupled to the ADC, wherein the correction circuit adjusts the output of its ADC to correct for DC offset and gain mismatch;

a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches; and

a multiplexer that is coupled to each ADC branch.

17. The apparatus of claim 16, wherein the PMOS transistor further comprises a first PMOS transistor, and wherein the bootstrap circuit further comprises:

a boost capacitor that is charged during a hold phase of the ADC;

a second PMOS transistor that is coupled to the boost capacitor at its source and the gate of the first PMOS switch at its drain;

a passgate circuit that is coupled to the delay circuit, that is coupled to the gate of the second PMOS transistor, and that receives the control voltage; and

a skew circuit that is coupled to sampling switch and that is controlled by the control voltage.

18. The apparatus of claim 17, wherein the passgate circuit further comprises:

a third PMOS transistor that is coupled to the controller at its source, the delay circuit at its gate, and the gate of the second PMOS transistor at its drain;

a first NMOS transistor that is coupled to the drain of the third PMOS transistor at its drain and the delay circuit at its gate; and

a second NMOS transistor that is coupled to the drain of the third PMOS transistor at its drain, the source of the first NMOS transistor at its source, and the gate of the first PMOS transistor at its gate.

19. The apparatus of claim 18, wherein the skew circuit further comprises a third NMOS transistor that is coupled to the gate of the first PMOS transistor at its drain and the controller at its gate.

20. The apparatus of claim 19, wherein the controller is a DAC or a charge pump.