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Track and hold architecture with tunable bandwidth

  • US 8,248,282 B2
  • Filed: 08/17/2010
  • Issued: 08/21/2012
  • Est. Priority Date: 08/17/2010
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a clock divider that receives a clock signal;

    a plurality analog-to-digital converter (ADC) branches that each receive an analog input signal, wherein each ADC branch includes;

    a delay circuit that is coupled to the clock divider;

    an ADC having;

    a bootstrap circuit that is coupled to the delay circuit;

    a sampling switch that is coupled to the bootstrap circuit; and

    a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated;

    a sampling capacitor that is coupled to the sampling switch; and

    an correction circuit that is coupled to the ADC; and

    a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches.

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