Semiconductor memory device

• US 8,248,864 B2
• Filed: 06/29/2010
• Issued: 08/21/2012
• Est. Priority Date: 07/27/2009
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ikeda, Hidetoshi, Takeda, Koichi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US12/801,859
• Publication Number:
  US 20110019493A1
• Time in Patent Office: 784 Days
• Field of Search: 365/189.05, 365/203, 365/207
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells that are connected to a word line and read data;

a plurality of bit line pairs that are connected respectively to the plurality of memory cells;

a precharge circuit that pre-charges the plurality of bit line pairs according to a precharge signal;

a column selector that selects one of the plurality of bit line pairs according to a column selection signal;

a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal;

a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit; and

an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal.

2. The semiconductor memory device according to claim 1, wherein the offset voltage adjustment circuit is connected to the output terminal pair of the sense amplifier circuit.

3. The semiconductor memory device according to claim 2, wherein the offset voltage adjustment circuit includes:

first and second load capacitors; and

first and second switch circuits that are respectively connected between the first and second load capacitors and the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal.

4. The semiconductor memory device according to claim 2, wherein the offset voltage adjustment circuit includes:

first and second inverters to which the weight control signal is input; and

first and second MOS transistors that have gate terminals respectively connected to the output terminal pair of the sense amplifier circuit and drain terminals and source terminals respectively connected to output terminals of the first and second inverters, and are controlled to turn on and off by output signals of the first and second inverters.

5. The semiconductor memory device according to claim 2, wherein the offset voltage adjustment circuit includes:

a first transistor that is connected between a first power supply terminal and one of the output terminal pair of the sense amplifier circuit, and has a control terminal connected to the other one of the output terminal pair of the sense amplifier circuit;

a second transistor that is connected between the first power supply terminal and the other one of the output terminal pair of the sense amplifier circuit, and has a control terminal connected to one of the output terminal pair of the sense amplifier circuit;

a first switch circuit that is connected between the first transistor and one of the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal; and

a second switch circuit that is connected between the second transistor and the other one of the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal.

6. The semiconductor memory device according to claim 1, wherein the offset voltage adjustment circuit is connected to the input terminal pair of the sense amplifier circuit.

7. The semiconductor memory device according to claim 6, wherein the sense amplifier circuit includes:

third and fourth transistors that have drive states controlled according to respective potential levels of the input terminal pair and output currents corresponding to the drive states to first and second nodes; and

a latch circuit that include first and second inverter circuits having outputs connected to inputs of one another and supplied with drive currents from the first and second nodes, and the offset voltage adjustment circuit includes;

a fifth transistor that is connected in parallel with the third transistor, has a drive state controlled according to a potential level of one of the input terminal pair, and outputs a current corresponding to the drive state to the first node;

a sixth transistor that is connected in parallel with the fourth transistor, has a drive state controlled according to a potential level of one of the input terminal pair, and outputs a current corresponding to the drive state to the second node;

a first switch circuit that is connected between the fifth transistor and the first node; and

a second switch circuit that is connected between the sixth transistor and the second node.

8. The semiconductor memory device according to claim 3, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

9. The semiconductor memory device according to claim 4, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second MOS transistors and turn off the other one of the first and second MOS transistors or to maintain current states of the first and second MOS transistors according to an output of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

10. The semiconductor memory device according to claim 5, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

11. The semiconductor memory device according to claim 7, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

12. The semiconductor memory device according to claim 3, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to turn off both of the first and second switch circuits according to an output of the sense amplifier circuit in a time delayed for a given period from activation timing of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

13. The semiconductor memory device according to claim 4, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second MOS transistors and turn off the other one of the first and second MOS transistors or to turn off both of the first and second MOS transistors according to an output of the sense amplifier circuit in a time delayed for a given period from activation timing of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

14. The semiconductor memory device according to claim 5, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to turn off both of the first and second switch circuits according to an output of the sense amplifier circuit in a time delayed for a given period from activation timing of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

15. The semiconductor memory device according to claim 7, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to turn off both of the first and second switch circuits according to an output of the sense amplifier circuit in a time delayed for a given period from activation timing of the sense amplifier circuit activated at substantially the same timing as activation of a word-line signal.

16. The semiconductor memory device according to claim 1, wherein the weight control circuit includes:

first and second latch circuits that output the weight control signal according to a weight control activation signal, a reset signal, and an output of the sense amplifier circuit, and

the first and second latch circuits

latch a value corresponding to an output of the sense amplifier circuit and output the value as the weight control signal when the weight control activation signal and the reset signal are in a combination of a first value,

hold the weight control signal regardless of an output value of the activated sense amplifier circuit when the weight control activation signal and the reset signal are in a combination of a second value, and

reset the weight control signal regardless of an output value of the activated sense amplifier circuit when the weight control activation signal and the reset signal are in a combination of a third value.

17. The semiconductor memory device according to claim 16, wherein the weight control circuit includes:

a first transition detector that is connected between one of the output terminal pair of the sense amplifier circuit and the first latch circuit; and

a second transition detector that is connected between the other one of the output terminal pair of the sense amplifier circuit and the second latch circuit, and

the first and second transition detectors respectively include inverter circuits with a logic threshold voltage set smaller than ½

of a power supply voltage.

18. The semiconductor memory device according to claim 17, wherein

the first and second latch circuits respectively include first to third NAND circuits,

the first NAND circuit has one input terminal to receive an output signal of the first or second transition detector and the other input terminal to receive the weight control activation signal, and outputs an operation result to one input terminal of the third NAND circuit,

the second NAND circuit has one input terminal to receive the reset signal and the other input terminal to receive an output signal of the third NAND circuit, and outputs an operation result to the other input terminal of the third NAND circuit, and

the third NAND circuit has one input terminal to receive an output signal of the first NAND circuit and the other input terminal to receive an output signal of the second NAND circuit, and outputs an operation result as the weight control signal.

19. The semiconductor memory device according to claim 3, wherein the offset voltage adjustment circuit includes:

third and fourth load capacitors respectively having smaller capacitance values than the first and second load capacitors; and

third and fourth switch circuits that are respectively connected between the third and fourth load capacitors and the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal.

20. The semiconductor memory device according to claim 4, wherein the offset voltage adjustment circuit includes:

third and fourth inverters to which the weight control signal is input; and

third and fourth MOS transistors respectively having smaller gate areas than the first and second MOS transistors, that have gate terminals respectively connected to the output terminal pair of the sense amplifier circuit and drain terminals and source terminals respectively connected to output terminals of the third and fourth inverters, and are controlled to turn on and off by output signals of the third and fourth inverters.

21. The semiconductor memory device according to claim 5, wherein the offset voltage adjustment circuit includes:

a seventh transistor that has a lower drive capability than the first transistor, is connected between the first power supply terminal and one of the output terminal pair of the sense amplifier circuit, and has a control terminal connected to the other one of the output terminal pair of the sense amplifier circuit;

an eighth transistor that has a lower drive capability than the second transistor, is connected between the first power supply terminal and the other one of the output terminal pair of the sense amplifier circuit, and has a control terminal connected to one of the output terminal pair of the sense amplifier circuit;

a third switch circuit that is connected between the seventh transistor and one of the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal; and

a fourth switch circuit that is connected between the eighth transistor and the other one of the output terminal pair of the sense amplifier circuit and controlled to turn on and off according to the weight control signal.

22. The semiconductor memory device according to claim 7, wherein the offset voltage adjustment circuit includes:

a seventh transistor that has a lower drive capability than the fifth transistor, is connected in parallel with the third transistor, has a drive state controlled according to a potential level of one of the input terminal pair, and outputs a current corresponding to the drive state to the first node;

an eighth transistor that has a lower drive capability than the sixth transistor, is connected in parallel with the fourth transistor, has a drive state controlled according to a potential level of one of the input terminal pair, and outputs a current corresponding to the drive state to the second node;

a third switch circuit that is connected between the seventh transistor and the first node; and

a fourth switch circuit that is connected between the eighth transistor and the second node.

23. The semiconductor memory device according to claim 19, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a first period at substantially the same timing as activation of a word-line signal, and outputs the weight control signal to turn on one of the third and fourth switch circuits and turn off the other one of the third and fourth switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a subsequent second period.

24. The semiconductor memory device according to claim 20, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second MOS transistors and turn off the other one of the first and second MOS transistors or to maintain current states of the first and second MOS transistors according to an output of the sense amplifier circuit activated during a first period at substantially the same timing as activation of a word-line signal, and outputs the weight control signal to turn on one of the third and fourth MOS transistors and turn off the other one of the third and fourth MOS transistors or to maintain current states of the third and fourth MOS transistors according to an output of the sense amplifier circuit activated during a subsequent second period.

25. The semiconductor memory device according to claim 21, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a first period at substantially the same timing as activation of a word-line signal, and outputs the weight control signal to turn on one of the third and fourth switch circuits and turn off the other one of the third and fourth switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a subsequent second period.

26. The semiconductor memory device according to claim 22, wherein the weight control circuit outputs the weight control signal to turn on one of the first and second switch circuits and turn off the other one of the first and second switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a first period at substantially the same timing as activation of a word-line signal, and outputs the weight control signal to turn on one of the third and fourth switch circuits and turn off the other one of the third and fourth switch circuits or to maintain current switch states according to an output of the sense amplifier circuit activated during a subsequent second period.

27. The semiconductor memory device according to claim 1, wherein the weight control circuit includes:

first to fourth latch circuits that output the weight control signal according to first and second weight control activation signals, a reset signal, and an output of the sense amplifier circuit,

the first latch circuit latches a value corresponding to one output of the sense amplifier circuit when the first and second weight control activation signals and the reset signal are in a combination of a first value,

the second latch circuit latches a value corresponding to one output of the sense amplifier circuit when the first and second weight control activation signals and the reset signal are in a combination of a second value,

the third latch circuit latches a value corresponding to the other output of the sense amplifier circuit when the first and second weight control activation signals and the reset signal are in a combination of the first value,

the fourth latch circuit latches a value corresponding to the other output of the sense amplifier circuit and outputs the value as the weight control signal when the first and second weight control activation signals and the reset signal are in a combination of the second value,

the first to fourth latch circuits

hold the weight control signal regardless of an output value of the activated sense amplifier circuit when the first and second weight control activation signals and the reset signal are in a combination of a third value, and

reset the weight control signal regardless of an output value of the activated sense amplifier circuit when the first and second weight control activation signals and the reset signal are in a combination of a fourth value.

28. The semiconductor memory device according to claim 27, wherein the weight control circuit includes:

a first transition detector that is connected between one of the output terminal pair of the sense amplifier circuit and the first and second latch circuits; and

a second transition detector that is connected between the other one of the output terminal pair of the sense amplifier circuit and the third and fourth latch circuits, and

the first and second transition detectors respectively include inverter circuits with a logic threshold voltage set smaller than ½

of a power supply voltage.

29. The semiconductor memory device according to claim 28, wherein

the first to fourth latch circuits respectively include first to third NAND circuits,

the first NAND circuit has one input terminal to receive an output signal of the first or second transition detector and the other input terminal to receive the first or second weight control activation signal, and outputs an operation result to one input terminal of the third NAND circuit,

the second NAND circuit has one input terminal to receive the reset signal and the other input terminal to receive an output signal of the third NAND circuit, and outputs an operation result to the other input terminal of the third NAND circuit, and

the third NAND circuit has one input terminal to receive an output signal of the first NAND circuit and the other input terminal to receive an output signal of the second NAND circuit, and outputs an operation result as the weight control signal.

30. The semiconductor memory device according to claim 1, wherein data of a bit line pair selected by the column selector is read after adjusting an offset voltage of the sense amplifier circuit.