All-digital timing control for multi-channel full-duplex transceiver

• US 8,248,974 B2
• Filed: 06/23/2009
• Issued: 08/21/2012
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lin, Chia-Liang
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): Wong, Blanche
• Application Number:
  US12/489,436
• Publication Number:
  US 20090323566A1
• Time in Patent Office: 1,155 Days
• Field of Search: None
• US Class Current: 370/286
• CPC Class Codes: H04L 2025/03636 Algorithms using least mean square [LMS]
• CPC Class Codes: H04L 25/03044 using fractionally spaced delay lines or combinations of fractionally integrally spaced taps
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 5/1469 using time-sharing
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0079 Receiver details

Abstract

A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a sampling rate converter for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals.

Claims

1. A method for controlling a timing for a multi-channel full-duplex transceiver, the method comprising the following steps:

generating a first clock and a second clock using a controlled oscillator in accordance with a control code, where a frequency of the second clock corresponds to a frequency of the first clock;

transmitting in parallel a plurality of outgoing signals onto a plurality of channels, respectively, in accordance with a timing defined by the first clock;

receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, in accordance with a timing defined by the second clock to generate in parallel a plurality of equalized signals, respectively;

converting in parallel said plurality of equalized signals into a plurality of refined signals, respectively, in accordance with a timing defined by the first clock; and

generating the control code, wherein in a first operation mode the control code is established by detecting a timing difference between an output clock of the controlled oscillator and a reference clock, and in a second operation mode the control code is established by detecting a timing embedded in one of said refined signals.

2. The method of claim 1, wherein the first clock is generated by dividing the output clock of the controlled oscillator by a factor of I, and the second clock is generated by dividing the output clock of the controlled oscillator by a factor of D;

wherein I and D are integers and I is greater than but prime to D.

3. The method of claim 1, wherein the timing difference between the output clock of the controlled oscillator and the reference clock is detected by a time-to-digital converter.

4. The method of claim 1, further comprising generating a plurality of soft decisions and a plurality of hard decisions for said plurality of refined signals, respectively.

5. The method of claim 4, wherein the timing embedded in one of said refined signals is detected using the soft decision and the hard decision associated with the one of said refined signals.

6. The method of claim 1, further comprising using a fractionally-spaced equalizer for equalizing in parallel said plurality of incoming signals.

7. The method of claim 1, further comprising using a plurality of echo cancellers for canceling the interference on said plurality of incoming signals from said plurality of outgoing signals.

8. The method of claim 1, further comprising using a sampling rate converter for converting in parallel said equalized signals into said plurality of refined signals.

9. The method of claim 1, wherein generating the control code further comprising performing a filtering function.

10. A multi-channel full-duplex transceiver comprising:

a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively, in accordance with a timing defined by a first clock;

a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, in accordance with a timing defined by a second clock to generate in parallel a plurality of equalized signals, respectively;

a plurality of sampling rate converters for converting in parallel said plurality of equalized signals into a plurality of refined signals, respectively, in accordance with a timing defined by the first clock; and

a clock generator for generating the first clock and second clock using a controlled oscillator based on a control code, wherein in a first operation mode the control code is established by detecting a timing difference between an output clock of the controlled oscillator and a reference clock, and in a second operation mode the control code is established by detecting a timing embedded in one of said refined signals.

11. The transceiver of claim 10, wherein the first clock is generated by dividing down the output clock of the controlled oscillator by a factor of I, and the second clock is generated by dividing the output clock of the controlled oscillator by a factor of D, where I and D are integers and I is greater than but prime to D.

12. The transceiver of claim 10, wherein the timing difference between the output clock of the controlled oscillator and the reference clock is detected by a time-to-digital converter.

13. The transceiver of claim 10, further comprising a plurality of decision devices for generating a plurality of soft decisions and a plurality of hard decisions for said plurality of refined signals, respectively.

14. The transceiver of claim 13, wherein the timing embedded in one of said refined signals is detected using the soft decision and the hard decision associated with the one of said refined signals.

15. The transceiver of claim 10, further comprising a fractionally-spaced equalizer for equalizing in parallel said plurality of incoming signals.

16. The transceiver of claim 10, further comprising a plurality of echo cancellers for canceling the interference on said plurality of incoming signals from said plurality of outgoing signals.

17. The transceiver of claim 10, wherein the all-digital phase lock loop further comprises a filter.

18. A multi-channel full-duplex transceiver comprising:

a clock generator for generating a first clock and a second clock using a controlled oscillator based on a control code, wherein the first clock and the second clock are dependent, wherein a first clock domain and a second clock domain are defined by the first clock and the second clock, respectively;

a plurality of transmitters, located in the first clock domain, for transmitting a plurality of outgoing signals onto a plurality of channels, respectively;

a plurality of receivers, located in the second clock domain, for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively;

a plurality of sampling rate converters, located between the first clock domain and the second clock domain, for converting in parallel said plurality of equalized signals into a plurality of refined signals, respectively.

19. The transceiver of claim 18, wherein the transceiver operates in a first operation mode or a second first operation mode according to the control code, wherein the control code is determined by whether the transceiver is a master transceiver or not.

20. The transceiver of claim 18, wherein in a first operation mode the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock, and in a second operation mode the control code is established by detecting a timing embedded in one of said refined signals.

21. The transceiver of claim 18, wherein the control code corresponds to at least one of the plurality of refined signals.