Clock and data recovery sampler calibration

• US 8,249,207 B1
• Filed: 02/29/2008
• Issued: 08/21/2012
• Est. Priority Date: 02/29/2008
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Hissen, Jurgen, Cartina, Dragos
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US12/040,585
• Time in Patent Office: 1,635 Days
• Field of Search: 375/316, 375/354, 375/355, 375373-376, 327/94, 327/95, 327/141, 327144-157
• US Class Current: 375/355
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and apparatus are disclosed, such as those involving clock and data recovery sampler calibration. One such method includes receiving an electronic data stream by a clock and data recovery (CDR) circuit comprising a data sampler and an edge sampler. The data stream includes data portions and transitioning portions. The method further includes conducting calibration of the CDR circuit. The calibration includes acquiring samples from the transitioning portions of the data stream using the data sampler; and calibrating the data sampler based at least partially on the samples acquired using the data sampler. The method allows one not only to improve performance, but also to improve yield and reduce testing and screening requirements without requiring any additional circuitry to detect the offsets and works with regular input signals.

Claims

1. A method of adjusting voltage offset in a receiver, the method comprising:

in a normal mode, synchronizing to a serial bit stream using one or more data samplers and one or more edge samplers, wherein the data samplers sample the serial bit stream in a data portion to retrieve data, and the edge samplers sample the serial bit stream in a transition portion for synchronization;

in an adjustment mode, using the same one or more data samplers to sample the transition portion to observe a voltage offset at an input of at least one of the one or more data samplers; and

compensating for the voltage offset of the one or more data samplers based at least partly on the observed voltage offsets.

2. The method of claim 1, wherein the adjustment mode further comprises:

oversampling a serial bit stream such that 3 consecutive samples correspond to a first data portion, a transition portion, and a second data portion, wherein at least the transition portion is sampled by a sampler from the one or more data samplers;

collecting a plurality of data sets of the 3 consecutive samples;

selecting data sets wherein the 3 consecutive samples correspond to 0 to 1, 1 to 0, or both 0 to 1 and 1 to 0 for the first data portion and the second data portion, respectively; and

adjusting timing based at least partly on data for the transition portions of the selected data sets.

3. The method of claim 1, further comprising compensating for the voltage offset such that an average of samples is adjusted in a direction towards 50% ones and 50% zeroes.

4. The method of claim 1, wherein compensating for the voltage offset comprises:

generating an average value from transition portions sampled by the one or more data samplers in the adjustment mode; and

compensating for the voltage offset based at least partly on the average value.

5. The method of claim 1, further comprising:

providing a first clock signal to the data samplers and a second clock signal to the edge samplers in the normal mode;

and providing the first clock signal to the edge samplers and the second clock signal to the data samplers in the adjustment mode.

6. The method of claim 1, wherein the adjustment mode is performed prior to the normal mode.

7. The method of claim 1, further comprising repetitively switching between the normal mode and the adjustment mode.

8. The method of claim 1, further comprising adjusting timing based at least partly on the indirectly observed voltage offsets to compensate for the voltage offset.

9. The method of claim 1, further comprising adding a correction factor to the data sampler to compensate for the voltage offset.

10. An apparatus comprising:

one or more data samplers coupled to a bit stream, the bit stream having data portions and transition portions;

one or more edge samplers coupled to the bit stream; and

a clock and data recovery circuit, wherein in a normal mode, the clock and data recovery circuit is configured to provide a data clock signal for the one or more data samplers for sampling of the data portions and to provide an edge clock signal for the one or more edge samplers for sampling of the transition portions, wherein in an adjustment mode, the clock and data recovery circuit is configured to provide the edge clock signal to the one or more data samplers to observe voltage offsets at inputs of the one or more data samplers, the clock and data recovery circuit being further configured to compensate for the voltage offsets based at least partly on the observed voltage offsets.

11. The apparatus of claim 10, wherein the data clock signal and the edge clock signal are different phases of the same clock signal.

12. The apparatus of claim 10, wherein the clock and data recovery circuit is further configured to swap the data clock signal and the edge clock signal for the normal mode and for the adjustment mode.

13. The apparatus of claim 10, wherein the data samplers and the edge samplers are configured to oversample a serial bit stream during the adjustment mode such that 3 consecutive samples correspond to a first data portion, a transition portion, and a second data portion,

wherein at least the transition portion is sampled by a sampler from the one or more data samplers,

wherein the clock and data recovery circuit is further configured to collect a plurality of data sets of the 3 consecutive samples, and to select data sets wherein the 3 consecutive samples correspond to 0 to 1, 1 to 0, or both 0 to 1 and 1 to 0 for the first data portion and the second data portion, respectively, and

wherein the clock and data recovery circuit is further configured to adjust timing based at least partly on data for the transition portions of the selected data sets.

14. The apparatus of claim 10, wherein the clock and data recovery circuit is further configured to compensate for the voltage offset such that an average of samples is adjusted in a direction towards 50% ones and 50% zeroes.

15. The apparatus of claim 10, wherein the data samplers are configured to sample the transition portions in the adjustment mode.

16. The apparatus of claim 15, wherein the clock and data recovery circuit is further configured to generate an average value from the transition portions sampled by the data samplers in the adjustment mode, and to compensate for the voltage offset, based at least partly on the average value.

17. The apparatus of claim 15, wherein the clock and data recovery circuit comprises a feedback loop having a polarity for timing sampling of the data samplers such that the data samplers sample the data portions in the normal mode, wherein the clock and data recovery circuit is further configured to invert the polarity of the feedback loop in the adjustment mode such that the data samplers sample the transition portions.

18. The apparatus of claim 17, wherein the clock and data recovery circuit comprises:

a phase detector configured to receive outputs from one of the data samplers and one of the edge samplers, and to output a first signal and a second signal; and

a phase filter including a first input and a second input, the phase filter being configured to receive the first and second signals at the first and second inputs, respectively, in the normal mode, the phase filter being further configured to receive the first signal at the second input and the second signal at the first input in the adjustment mode.

19. The apparatus of claim 17, wherein the phase filter is further configured to provide a phase selection code at least partly in response to the first and second signals, wherein the clock and data recovery circuit further comprises a phase picker configured to provide a first clock signal and a second clock signal at least partly in response to the phase selection code, and wherein the data samplers and edge samplers are configured to be synchronized with the first and second clock signals, respectively, in the normal mode.

20. The apparatus of claim 19, wherein the data samplers are configured to be synchronized with the second clock signal in the adjustment mode, wherein the edge samplers are configured to be synchronized with the first clock signal in the adjustment mode.

21. The apparatus of claim 10, wherein at least one of the data samplers is configured to take a plurality of samples during a period of the data clock signal.

22. The apparatus of claim 10, wherein the clock and data recovery circuit is further configured to adjust at least one of the data clock signal or the edge clock signal to compensate for the observed voltage offsets.

23. The apparatus of claim 10, wherein the clock and data recovery circuit is further configured to add a correction factor to the data sampler to compensate for the voltage offsets.