Command and interrupt grouping for a data storage device

• US 8,250,271 B2
• Filed: 08/07/2009
• Issued: 08/21/2012
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Swing, Andrew T., Borchers, Albert T., Grundler, Grant
• Primary Examiner(s): Misiura, Brian
• Assistant Examiner(s): Huynh, Kim
• Application Number:
  US12/537,727
• Publication Number:
  US 20100262738A1
• Time in Patent Office: 1,110 Days
• Field of Search: 710260-269, 710240-244, 710/22, 710/200, 711/106, 711/154
• US Class Current: 710/260
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device may include multiple memory chips and a controller that is operably coupled to the memory chips and that is arranged and configured to receive a group of commands from a host, where each of the commands in the group includes a same group number to identify the commands as part of the group, process the group of the commands using the memory chips and generate and send a single interrupt to the host when the group of the commands completes processing.

Claims

1. A data storage device, comprising:

multiple memory chips; and

a controller that is operably coupled to the memory chips and that is arranged and configured to;

receive multiple groups of commands from a host, wherein each group of commands is assigned a group number and each command in a specific group includes a same group number to identify the commands as part of the specific group,

process the groups of the commands using the memory chips, and

generate and send a single interrupt to the host for each of the groups when each of the groups of the commands completes processing,

wherein the controller is capable of maintaining an order of the commands within a same group designated for a same storage location and, at a same time, is capable of reordering and dispatching commands from different groups designated for different storage locations in a non-contiguous order.

2. The data storage device of claim 1 wherein each of the commands includes a command header and the command header includes the group number.

3. The data storage device of claim 1 wherein a last command in the group of the commands includes a flag in a command header to indicate the last command to the controller.

4. The data storage device of claim 1 wherein the group number identifies each of the commands as part of the group without using pointers in the commands to point to a next command in the group.

5. The data storage device of claim 1 wherein the controller comprises an interrupt processor that is arranged and configured to track the group of the commands as the commands are processed by the controller and to generate the single interrupt to send to the host when the group of the commands is completed processing.

6. The data storage device of claim 5 wherein the interrupt processor comprises multiple counters, wherein each of the counters is assigned to a different group of commands received by the controller.

7. The data storage device of claim 5 wherein the interrupt processor comprises multiple different interrupt mechanisms.

8. The data storage device of claim 7 wherein more than one interrupt mechanism is enabled at a same time.

9. The data storage device of claim 7 wherein the interrupt mechanisms include a watermark interrupt mechanism, a timeout interrupt mechanism and a group interrupt mechanism.

10. The data storage device of claim 1 wherein the memory chips are flash memory chips and the controller is a field programmable gate array (FPGA) controller.

11. The data storage device of claim 10 further comprising:

a memory board on which the flash memory chips are arranged and configured into multiple channels, with each of the channels being associated with one or more of the flash memory chips; and

a controller board that is operably connected to the memory board, wherein the controller board comprises;

a high speed interface; and

the controller that is arranged and configured to receive the commands from the host using the high speed interface.

12. A method for processing a group of commands on a data storage device having multiple memory chips, the method comprising:

receiving multiple groups of commands from a host, wherein each group of commands is assigned a group number and each command in a specific group includes a same group number to identify the commands as part of the specific group;

processing the groups of commands using multiple memory chips; and

generating and sending a single interrupt to the host for each of the groups when each of the groups of the commands completes processing, wherein processing the groups of commands includes maintaining an order of the commands within a same group designated for a same storage location and, at a same time, reordering and dispatching commands from different groups designated for different storage locations in a non-contiguous order.

26. The method as in claim 12 wherein the memory chips are flash memory chips.

27. The method as in claim 12 wherein each of the commands includes a command header and the command header includes the group number inserted by the host.

28. The method as in claim 12 further comprising:

incrementing a group counter when a command in a group of commands begins processing; and

decrementing the group counter when a command in the group of commands completes processing.

13. An apparatus for tracking commands in a controller, the apparatus comprising:

multiple group counters, wherein each of the group counters is configured to track a group of commands being processed by a controller by incrementing when a command in the group begins processing by the controller and decrementing when a command in the group completes processing; and

interrupt send logic that is operably coupled to the group counters and that is arranged and configured to generate and send a single interrupt for each of the group counters when all of the commands in a group complete processing,

wherein the controller is capable of maintaining an order of the commands within a same group designated for a same storage location and, at a same time, is capable of reordering and dispatching commands from different groups designated for different storage locations in a non-contiguous order.

14. The apparatus of claim 13 wherein each of the commands in a same group is identified by a same group number.

15. The apparatus of claim 13 wherein the multiple group counters are configured to receive a signal to increment one of the group counters when a command being tracked by the group counter begins processing.

16. The apparatus of claim 13 wherein the multiple group counters are configured to receive a signal to decrement one of the group counters when a command being tracked by the group counter completes processing.

17. The apparatus of claim 13 wherein the interrupt send logic is configured to generate and send the single interrupt when a last command in a group begins processing and the group counter associated with the final command is decremented to zero.

18. A method for tracking commands in a controller, the method comprising:

incrementing a group counter when a command in a group of commands begins processing;

decrementing the group counter when a command in the group of commands completes processing;

generating and sending a single interrupt for the group of commands when all of the commands in the group complete processing; and

maintaining an order of the commands within a same group designated for a same storage location and, at a same time, reordering and dispatching commands from different groups designated for different storage locations in a non-contiguous order.

19. The method as in claim 18 wherein generating and sending the single interrupt comprises generating and sending the single interrupt when a last command in the group begins processing and the group counter is decremented to zero.

29. The method as in claim 18 wherein the controller is a field programmable gate array (FPGA) controller.

30. The method as in claim 19 further comprising using a flag in the last command to indicate the last command in the group.

20. A system comprising:

a data storage device including a plurality of memory chips and multiple physical channels for communication of data between a host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips; and

a host operably coupled to the data storage device using an interface, the host comprising a driver that is configured to;

send commands to the data storage device for processing by the data storage device using the plurality of memory chips,

group the commands into one or more different groups and to assign a group number to each of the commands in a group, and

mark a last command in a group,

wherein the data storage device is capable of maintaining an order of the commands within a same group designated for a same storage location and, at a same time, is capable of reordering and dispatching commands from different groups designated for different storage locations in a non-contiguous order.

21. The system of claim 20 wherein the data storage device is configured to generate and send a single interrupt to the host after processing the commands in the group.

22. The system of claim 20 wherein the plurality of memory chips comprise flash memory chips.

23. The system of claim 20 wherein the driver is configured to track usage of group numbers.

24. The system of claim 20 where the host is configured to enable one or more interrupt mechanisms on the data storage device.

25. The system of claim 24 wherein the interrupt mechanisms include a watermark interrupt mechanism, a timeout interrupt mechanism and a group interrupt mechanism.