High bandwidth memory interface
First Claim
1. A Dynamic Random Access Memory (DRAM) controller configured for communication with at least one semiconductor device over an interface, the controller comprising:
- a) data terminals for coupling to the interface and for providing data signals for transmission to the semiconductor device;
b) at least one data clock terminal for coupling to the interface and for providing at least one data clock signal for transmission to the semiconductor device;
c) output drivers for driving said data signals and said at least one data clock signal on said data terminals and said data clock terminal, respectively; and
d) polysilicon termination resistors coupled to each of said data and data clock terminals, and said polysilicon termination resistors are within said DRAM controller and integrated with said DRAM controller on a semiconductor chip.
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Accused Products
Abstract
This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.
32 Citations
42 Claims
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1. A Dynamic Random Access Memory (DRAM) controller configured for communication with at least one semiconductor device over an interface, the controller comprising:
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a) data terminals for coupling to the interface and for providing data signals for transmission to the semiconductor device; b) at least one data clock terminal for coupling to the interface and for providing at least one data clock signal for transmission to the semiconductor device; c) output drivers for driving said data signals and said at least one data clock signal on said data terminals and said data clock terminal, respectively; and d) polysilicon termination resistors coupled to each of said data and data clock terminals, and said polysilicon termination resistors are within said DRAM controller and integrated with said DRAM controller on a semiconductor chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A Dynamic Random Access Memory (DRAM) system comprising:
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a) at least one DRAM including polysilicon termination resistors within said DRAM and integrated with said DRAM on a semiconductor chip; b) a DRAM controller; and c) a data bus having said polysilicon termination resistors coupled to it, said data bus for providing write data from said DRAM controller to said DRAM, and for providing read data from said DRAM to said DRAM controller. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A Dynamic Random Access Memory (DRAM) comprising:
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a) a first terminal for coupling to a clock line; b) a plurality of second terminals for coupling to a command bus providing address and control information to the DRAM, said clock line and said command bus comprising a source synchronous bus; c) polysilicon termination resistors coupled to said plurality of second terminals, and said polysilicon termination resistors are within the DRAM and integrated with the DRAM on a single chip. - View Dependent Claims (27, 28)
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29. In a memory controller, a method for synchronization comprising:
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a) employing polysilicon resistors integrated with the memory controller on a semiconductor chip to resistively terminate data bus terminals and data clock terminals of the memory controller; b) receiving data clock signals on said data clock terminals; c) generating a data sampling clock with said received data clock signals; d) receiving read data signals on said data bus terminals; and e) sampling the received read data signals with said data sampling clock so that the data input to the device is synchronized with the data clock signals. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification