Control of data accesses to a cache in data processing

• US 8,250,309 B2
• Filed: 01/28/2005
• Issued: 08/21/2012
• Est. Priority Date: 02/16/2004
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: McGlew, Patrick Gerard, Burdass, Andrew
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US11/044,260
• Publication Number:
  US 20050182905A1
• Time in Patent Office: 2,762 Days
• Field of Search: 711/118, 711/144, 711/119, 711/145, 711/138
• US Class Current: 711/145
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass

Abstract

A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predetermined value and not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value.

Claims

1. A data processor comprising:

a control register configured to store a cache control value;

data accessing logic, responsive to a data access instruction and to said cache control value, configured to look for data to be accessed in a cache if said cache control value has a predetermined value and to not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value;

a further cache control value, said data accessing logic, responsive to a data access instruction and to both said cache control value and said further cache control value, configured to look for data to be accessed in a cache if said cache control value has a predetermined value and said further cache control value does not have a second predetermined value and to not to look for said data to be accessed in said cache if either said cache control value does not have said predetermined value or said further cache control value has said second predetermined value, said data processor configured to set said further cache control value to have said second predetermined value in response to a detected predetermined state of said data processor and to re-evaluate said further cache control value in response to said data processor detecting said data processor leaving said predetermined state, said predetermined state comprising execution of a sequence of data access instructions accessing a memory region that is not cacheable.

2. A data processor according to claim 1, said data processor detecting said data processor leaving said predetermined state in response to a memory access instruction being an access to a different region of memory.

3. A data processor according to claim 1, said data processor detecting said data processor leaving said predetermined state in response to a memory access instruction giving a memory region miss.

4. A data processor according to claim 3, said data processor being operable to re-issue memory access instructions giving a memory region miss following re-evaluation of said cache control value.

5. A method of data processing comprising the steps of:

storing a cache control value within a control register;

in response to a data access instruction and to said cache control value, reading a cache if said cache control value has a predetermined value and not reading said cache if said cache control value does not have said predetermined value, wherein said data processor comprises a further cache control value;

reading, in response to a data access instruction and to both said cache control value and said further cache control value, a cache if said cache control value has a predetermined value and said further cache control value does not have a second predetermined value and not reading said cache if either said cache control value does not have said predetermined value or said further cache control value has said second predetermined value; and

setting said further cache control value to have said second predetermined value in response to a detected predetermined state of said data processor and re-evaluating said further cache control value in response to detecting said data processor leaving said predetermined state, said predetermined state comprising execution by said data processor of a sequence of data access instructions accessing a memory region that is not cacheable.

6. A method according to claim 5, said method detecting said data processor leaving said predetermined state in response to a memory access instruction being an access to a different region of memory.

7. A method according to claim 5, said data processor detecting said data processor leaving said predetermined state in response to a memory access instruction giving a memory region miss.

8. A method according to claim 7, said method re-issuing memory access instructions giving a memory region miss following re-evaluation of said cache control value.