Operating system virtual memory management for hardware transactional memory

• US 8,250,331 B2
• Filed: 06/26/2009
• Issued: 08/21/2012
• Est. Priority Date: 06/26/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Yamada, Koichi, Sheaffer, Gad, Adl-Tabatabai, Ali-Reza, Wang, Landy, Taillefer, Martin, Kishan, Arun, Callahan, David, Gray, Jan, Bassin, Vadim
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Ayash, Marwan
• Application Number:
  US12/493,161
• Publication Number:
  US 20100332721A1
• Time in Patent Office: 1,152 Days
• Field of Search: None
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Claims

1. A method comprising:

at a first hardware thread, an operating system in kernel mode allocating a first virtual page causing the first virtual page to be mapped to a first physical page in a virtual memory page table;

an application running on the first hardware thread beginning a hardware transaction, such that read or write operations performed while in the transaction implicitly have transactional memory hardware state established when data is read from or written to data cache entries, wherein the data cache entries are correlated to physical addresses in the first physical page, and in the application, the first thread accessing a virtual address within the first virtual page which generates a page fault;

the first hardware thread performing a user to kernel mode transition caused by the page fault incurring the user to kernel mode transition;

as a result of the first hardware thread performing a user to kernel mode transition, the transactional memory hardware automatically suspending implicitly correlating transactional memory hardware state in cache entries when data is read or written to cache entries for the first thread;

then the first hardware thread performing a kernel to user mode transition back to user mode;

as a result of the first hardware thread performing a kernel to user mode transition, the transactional memory hardware automatically resuming implicit correlating of transactional memory hardware state in cache entries when data is read or written to cache entries for the first thread; and

wherein the transactional memory hardware state is not automatically flushed as a result of the first hardware thread performing a user to kernel mode transition, the first hardware thread performing a kernel to user mode transition back to user mode, or the execution of instructions while in kernel mode.

2. The method of claim 1, wherein the transactional memory hardware state comprises at least one of memory access conflict monitoring, buffering or metadata properties in cache entries.

3. The method of claim 1, wherein as a result of resuming implicit correlating of transactional memory hardware state in cache entries when data is read or written to cache entries for the first thread, the first thread:

resuming the hardware transaction without incurring a transaction abort; and

then completing the transaction, including committing buffered write data for one or more buffered cache entries in the first physical page.

4. The method of claim 1, wherein the first hardware thread performing a user to kernel mode transition being performed as the result of:

the operating system deciding to unmap the first virtual page which maps to the first physical page, the first physical page containing transactional memory hardware state created by the first thread, and as a result, the operating system removing the mapping of the first virtual page to the first physical page from the virtual memory page table and performing actions to reload virtual memory management hardware with an updated mapping for the first virtual page.

5. The method of claim 4, wherein the operating system that decides to unmap the first virtual page is running on a different thread than the first thread.

6. The method of claim 4, further comprising:

the operating system reestablishing the virtual memory mapping from the first virtual page to the first physical page and performing actions to reload virtual memory management hardware with an updated mapping for the first virtual page, and returning from the page fault to resume execution of the first thread.

7. The method of claim 1, further comprising while in kernel mode the transactional memory hardware continuing to monitor for conflicting memory accesses by other agents, and an access occurring which conflicts, thus setting an indicator, and further comprising upon returning to user mode, and as a result of the indicator being set, aborting the transaction.