Hardware wake-and-go mechanism for a data processing system
First Claim
1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
- examining, by a hardware wake-and-go mechanism within a processor, an instruction stream for a thread as the instruction stream is being pre-fetched;
recognizing by the hardware wake-and-go mechanism, a programming idiom in the instruction stream that indicates the thread is waiting for an event that writes a data value to a target address;
populating, by the hardware wake-and-go mechanism, a wake-and-go storage array with the target address;
placing the thread in a sleep state;
responsive to the event that writes the data value to the target address, determining whether to wake the thread; and
in response to a determination that the thread is to be awoken, placing the thread in a non-sleep state.
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Accused Products
Abstract
A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
233 Citations
20 Claims
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1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
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examining, by a hardware wake-and-go mechanism within a processor, an instruction stream for a thread as the instruction stream is being pre-fetched; recognizing by the hardware wake-and-go mechanism, a programming idiom in the instruction stream that indicates the thread is waiting for an event that writes a data value to a target address; populating, by the hardware wake-and-go mechanism, a wake-and-go storage array with the target address; placing the thread in a sleep state; responsive to the event that writes the data value to the target address, determining whether to wake the thread; and in response to a determination that the thread is to be awoken, placing the thread in a non-sleep state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processing system, comprising:
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a hardware wake-and-go mechanism; and a wake-and-go array, wherein the hardware wake-and-go mechanism is configured to; examine an instruction stream for a thread as the instruction stream is being pre-fetched; recognize a programming idiom in the instruction stream that indicates the thread is waiting for an event that writes a data value to a target address; populate the wake-and-go storage array with the target address; place the thread in a sleep state; responsive to the event that writes the data value to the target address, determine whether to wake the thread; and in response to a determination that the thread is to be awoken, place the thread in a non-sleep state. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A hardware wake-and-go mechanism, comprising:
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a wake-and-go storage array; and wake-and-go logic, wherein the wake-and-go logic is configured to; examine an instruction stream for a thread as the instruction stream is being pre-fetched; recognize a programming idiom in the instruction stream that indicates the thread is waiting for an event that writes a data value to a target address; populate the wake-and-go storage array with the target address; place the thread in a sleep state; responsive to the event that writes the data value to the target address, determine whether to wake the thread; and in response to a determination that the thread is to be awoken, place the thread in a non-sleep state. - View Dependent Claims (17, 18, 19, 20)
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Specification