Hardware definition method including determining whether to implement a function as hardware or software

• US 8,250,503 B2
• Filed: 01/17/2007
• Issued: 08/21/2012
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, May, Frank
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US12/087,916
• Publication Number:
  US 20090199167A1
• Time in Patent Office: 2,043 Days
• Field of Search: 716101-104
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

A hardware definition system and method includes a computer processor analyzing software function modules of a software program, and generating, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library.

Claims

1. A computer-implemented hardware definition method, the method comprising:

analyzing, by a computer processor, software function modules of a software program; and

generating, by the processor, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library that includes at least one parameterizable, executable modules;

wherein the generating, for each of at least one of the software function modules, includes;

selecting a plurality of hardware modules from the hardware module library based on respective parameters of the respective hardware modules that correspond to the analyzed software function module;

combining the selected plurality of hardware modules; and

optimizing the combined hardware modules.

2. A computer-implemented hardware definition method, the method comprising:

analyzing, by a computer processor, software function modules of a software program; and

generating, by the processor, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library.

3. The method according to claim 2, wherein at least one of the respective hardware modules is a non-programmable module whose function is fixed.

4. The method according to either of claims 2 and 3, wherein at least one of the respective hardware modules is programmable in its function.

5. The method according to claim 4, further comprising:

converting those of the software function modules set in the generating step to be implemented as a respective hardware module into the respective hardware modules.

6. The method according to claim 5, further comprising:

adding definitions of the converted software function modules to at least one of the hardware module library and a chip definition file.

7. The method according to claim 6, further comprising:

forming a chip based on a combination of the modules in the chip definition file.

8. The method according to claim 7, wherein the forming of the chip includes inserting communication channels, as defined in the chip definition file, between the hardware modules that are combined.

9. The method according to claim 8, further comprising inserting memory units into at least some of the communication channels.

10. The method according to claim 9, wherein at least one of the memory units is a register.

11. The method according to claim 9, wherein at least one of the memory units is a first-in-first-out (FIFO) memory unit.

12. The method according to claim 9, wherein at least one of the memory units is a Random-Access-Memory.

13. The method according to claim 5, wherein the converting includes generating a hardware description language.

14. The method according to claim 5, wherein the converting includes generating a hardware netlist.

15. The method according to claim 5, wherein the converting includes synthesizing the respective hardware modules.

16. The method according to claim 15, wherein the synthesizing includes setting at least one of a processing time, a path delay, and a signal delay constraint.

17. The method according to claim 5, wherein the respective hardware modules are added to the hardware module library.

18. The method according to claim 4, further comprising:

optimizing each of one or more of the software function modules for execution as a non-programmable hardware module whose function is fixed.

19. The method according to claim 18, further comprising:

for each of the optimized one or more of the software function modules, selecting a suitable one of the hardware modules defined in the module library.

20. The method according to claim 19, further comprising:

adding the selected hardware modules to a chip definition file.

21. The method according to claim 20, further comprising:

forming a chip based on a combination of the modules in the chip definition file.

22. The method according to claim 21, wherein the forming of the chip includes inserting communication channels, as defined in the chip definition file, between the hardware modules that are combined.

23. The method according to claim 22, further comprising inserting memory units into at least some of the communication channels.

24. The method according to claim 23, wherein at least one of the memory units is a register.

25. The method according to claim 23, wherein at least one of the memory units is a first-in-first-out (FIFO) memory unit.

26. The method according to claim 23, wherein at least one of the memory units is a Random-Access-Memory.

27. The method according to claim 4, further comprising:

compiling each of one or more of the software function modules into executable code for at least one of a microprocessor and a microcontroller.

28. The method according to claim 27, further comprising:

selecting, for the executable code and from the hardware module library, hardware modules capable of performing the functions required by the executable code.

29. The method according to claim 27, wherein the selecting includes modifying a function required by the executable code to correspond to a function of a module of the hardware module library that is more efficient than the function required by the executable code prior to the modification.

30. The method according to claim 4, further comprising:

for each of one or more of the software function modules whose setting indicates that the respective software function module is to be implemented as a software module, selecting a suitable one of the hardware modules defined in the module library for its execution.

31. The method according to claim 30, further comprising:

adding the selected hardware modules to a chip definition file.

32. The method according to claim 31, further comprising:

forming a chip based on a combination of the modules in the chip definition file.

33. The method according to claim 32, wherein the forming of the chip includes inserting communication channels, as defined in the chip definition file, between the hardware modules that are combined.

34. The method according to claim 33, further comprising inserting memory units into at least some of the communication channels.

35. The method according to claim 34, wherein at least one of the memory units is a register.

36. The method according to claim 34, wherein at least one of the memory units is a first-in-first-out (FIFO) memory unit.

37. The method according to claim 34, wherein at least one of the memory units is a Random-Access-Memory.

38. The method according to claim 3, further comprising:

for each of one or more of the software function modules whose setting indicates that the respective software function module is to be implemented as a hardware module, selecting a suitable one of the non-programmable hardware modules defined in the module library for its execution.

39. The method according to claim 38, further comprising:

adding the selected hardware modules to a chip definition file.

40. The method according to claim 39, further comprising:

forming a chip based on a combination of the modules in the chip definition file.

41. The method according to claim 40, wherein the forming of the chip includes inserting communication channels, as defined in the chip definition file, between the hardware modules that are combined.

42. The method according to claim 41, further comprising inserting memory units into at least some of the communication channels.

43. The method according to claim 42, wherein at least one of the memory units is a register.

44. The method according to claim 42, wherein at least one of the memory units is a first-in-first-out (FIFO) memory unit.

45. The method according to claim 42, wherein at least one of the memory units is a Random-Access-Memory.

46. The method according to claim 2, wherein source code written in a high level programming language is compiled into at least a subset of the software function modules.

47. The method according to claim 2, wherein source code written in one of a low level programming language and an assembly language is compiled into at least a subset of the software function modules.

48. The method according to claim 2, wherein the analyzing includes determining whether any of the software function modules does not meet at least one of a maximum power requirement, a performance requirement, and a maximum chip area requirement.

49. The method according to claim 2, wherein the analyzing includes determining which of the software function modules is estimated to execute with a low performance when implemented as a software module executed on a hardware module whose function is programmable.

50. The method according to claim 2, wherein the analyzing includes analyzing respective required clock frequencies of the software function modules.

51. The method according to claim 2, wherein the analyzing includes analyzing respective frequencies of execution of the software function modules.

52. The method according to claim 51, where the analyzing includes analyzing ratios of frequencies of execution of different ones of the software function module to each other.

53. The method according to claim 2, wherein the analyzing includes analyzing respective power dissipations of the software function modules.

54. The method according to claim 2, wherein the hardware module library includes at least one parameterizable, executable module.

55. The method according to claim 54, wherein the generating, for each of at least one of the software function modules, includes selecting a hardware module from the hardware module library based on a parameter of the respective hardware module that corresponds to the respective analyzed software function module.