Thin film transistor array panel and method for manufacturing the same

• US 8,252,639 B2
• Filed: 11/22/2010
• Issued: 08/28/2012
• Est. Priority Date: 09/24/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Je-Hun, Cho, Beom-Seok, Jeong, Chang-Oh, Kim, Joo-Han
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US12/951,981
• Publication Number:
  US 20110065220A1
• Time in Patent Office: 645 Days
• Field of Search: 438/149, 438/151, 438/158, 438/162, 438/161, 438/164, 438/585, 438/586, 438/597, 438/653
• US Class Current: 438/158
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode

Abstract

The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Claims

1. A manufacturing method of a thin film transistor array panel, comprising:

forming a gate line on an insulating substrate;

depositing a gate insulating layer and a first a-Si layer in sequence;

depositing a second a-Si layer doped with a conductive impurity on the first a-Si layer and a third a-Si layer including nitrogen on the second a-Si layer;

patterning the third a-Si layer, the second a-Si layer, and the first a-Si layer to form a pre-diffusion barrier, pre-ohmic contacts, and a semiconductor layer, respectively;

forming a data line and a drain electrode partially overlapping the pre-diffusion barrier;

etching the pre-diffusion barrier and the pre-ohmic contacts disposed between the data line and the drain electrode to form diffusion barriers and ohmic contacts, respectively; and

forming a pixel electrode electrically connected to the drain electrode.

2. The method of claim 1, wherein the data line and the drain electrode comprise first to third conductor layers, the first and third conductor layers comprising Mo or a Mo alloy, and the second layer comprising Al or an Al alloy.

3. The method of claim 1, wherein the third a-Si layer is deposited in a same environment as the second a-Si layer except that the third a-Si layer is deposited in an environment that includes a gas containing nitrogen.

4. The method of claim 3, wherein the gas containing nitrogen is one of N₂, NH₃, and a mixture of N₂ and NH₃.

5. The method of claim 1, further comprising forming color filters before forming the pixel electrode.