Method for forming a nonvolatile memory cell comprising a reduced height vertical diode

• US 8,252,644 B2
• Filed: 09/08/2011
• Issued: 08/28/2012
• Est. Priority Date: 12/19/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, Scott Brad, Radigan, Steven J.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/228,109
• Publication Number:
  US 20110318911A1
• Time in Patent Office: 355 Days
• Field of Search: 438257-258, 438/700, 438125-132, 438/237, 257313-316
• US Class Current: 438/258
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF₂ ions. Numerous additional aspects are provided.

Claims

1. A method for forming a nonvolatile memory cell, the method comprising:

forming a rail-shaped first conductor above a substrate;

forming a rail-shaped second conductor above the first conductor; and

forming a substantially vertical first pillar disposed between the first conductor and the second conductor,

wherein the first pillar comprises a vertically oriented p-i-n diode, and the p-i-n diode comprises;

a) a bottom heavily doped region having a first conductivity type,

b) a middle intrinsic or lightly doped region, and

c) a top heavily doped region having a second conductivity type opposite the first conductivity type,

wherein the bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF₂ ions.

2. The method of claim 1, further comprising forming a dielectric layer between the first diode and the second conductor.

3. The method of claim 2, wherein the dielectric layer comprises an oxide, nitride, or oxynitride.

4. The method of claim 2, wherein the dielectric layer is silicon dioxide.

5. The method of claim 1, wherein the nonvolatile memory cell resides in a monolithic three dimensional memory array.

6. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a plurality of substantially parallel, substantially coplanar rail-shaped first conductors above a substrate;

forming a plurality of substantially parallel, substantially coplanar rail-shaped second conductors above the first conductors; and

forming a plurality of substantially vertical first pillars;

wherein each first pillar is disposed between one of the first conductors and one of the second conductors;

wherein each of the first pillars comprises a vertically oriented p-i-n diode; and

wherein each p-i-n diode comprises;

a) a bottom heavily doped region having a first conductivity type;

b) a middle intrinsic or lightly doped region; and

c) a top heavily doped region having a second conductivity type opposite the first conductivity type;

wherein the bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF₂ ions.

7. The method of claim 6, further comprising forming:

forming a plurality of substantially vertical second pillars above the first pillars; and

forming a plurality of substantially parallel, substantially coplanar rail-shaped third conductors above the second conductors.

8. The method of claim 7, wherein each of the second pillars is disposed between one of the second conductors and one of the third conductors.

9. The method of claim 7, further comprising forming a plurality of substantially parallel, substantially coplanar rail-shaped fourth conductors above the third conductors, wherein each of the second pillars is disposed between one of the third conductors and one of the fourth conductors.