Fabrication of trench DMOS device having thick bottom shielding oxide

• US 8,252,647 B2
• Filed: 08/31/2009
• Issued: 08/28/2012
• Est. Priority Date: 08/31/2009
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Lee, Yeeheng, Tai, Sung-Shan, Chang, Hong, Chen, John
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US12/551,417
• Publication Number:
  US 20110049618A1
• Time in Patent Office: 1,093 Days
• Field of Search: 438/142, 438/197, 438/259, 438/268, 438/270, 257/E29.26, 257/E29.257
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

Claims

1. A method for fabricating a semiconductor device comprising:

a) forming a trench in the semiconductor layer;

b) forming an oxide-nitride-oxide (ONO) structure on a sidewall and at a bottom of the trench, wherein the ONO structure includes a nitride layer between first and second oxide layers, wherein forming the ONO structure includes forming a first oxide layer on the sidewall and at the bottom of the trench and on top of the semiconductor layer;

forming a nitride layer on top of the first oxide layer; and

forming a second oxide layer on top of the nitride layer; and

c) forming one or more conductive structures in a portion of the trench not occupied by the ONO structure, wherein the one or more conductive structures include a shield gate structure having an insulating material sandwiched between a first conductive structure and a second conductive structure, wherein forming the second oxide layer includes;

filling the trench with the second oxide layer;

etching back the second oxide layer to leave a portion of the second oxide at the bottom of the trench;

forming a spacer layer with the predetermined thickness T1 on the second oxide layer and on the sidewalls of the remaining portions of the trench;

anisotropically etching the spacer layer to form one or more spacers on the sidewall;

anisotropically etching the second oxide layer to a non-zero thickness T2 at the bottom of the trench; and

removing the one or more spacers.

2. The method of claim 1 wherein c) comprises:

filling the trench with the first conductive structure;

etching back the first conductive structure to below a top surface of the second oxide layer;

forming a reoxidation layer on top of the first conductive structure;

removing the first oxide layer, the nitride layer and the third oxide layer exposed at the sidewall of the trench and at the top of the semiconductor layer;

forming a gate oxide at the sidewall of the trench and at the top of the semiconductor layer; and

filling the remaining of the trench with the second conductive structure and etching back the second conductive structure.

3. The method of claim 1 wherein c) comprises:

filling a portion at the bottom of the trench with the first conductive structure;

forming a reoxidation layer on top of the first conductive structure in the trench;

removing the second oxide and the nitride layer exposed in the trench;

forming a gate oxide on the sidewall of the trench; and

filling a remaining portion of the trench with the second conductive structure and etching back the second conductive structure.

4. The method of claim 1 further comprising:

d) forming a first polysilicon region on the ONO at the bottom of the trench, wherein the top of the first polysilicon region is below the top of the trench;

e) growing an inter polysilicon oxide (IPO) on top of the first polysilicon region;

f) removing the top portions of the ONO, wherein a part of the IPO still remains after this step;

g) forming a gate dielectric on the remaining sidewalls of the trench; and

h) filling the remaining portions of the trench with a gate electrode to form a shield gate trench.

5. The method of claim 4 further comprising, before e):

implanting the top of the first polysilicon region to improve said growing IPO.

6. A method for fabricating a semiconductor device comprising:

a) forming a first trench of width A in a semiconductor layer;

b) filling the first trench with an insulating material;

c) removing selected portions of the insulating material leaving a remaining portion of the insulating material on a bottom surface and sidewalls of the first trench;

d) forming one or more spacers with a predetermined thickness T1 on one or more sidewalls of a remaining portion of the first trench;

e) anisotropically etching the remaining portion of the insulating material using the one or more spacers as a mask to form a second trench in the insulating material having a predetermined thickness T2 at a bottom thereof and a width A′

determined by the thickness T1 of the spacers, wherein A′

is less than A, wherein some of the insulating material remains on the bottom surface and sidewalls of the first trench after said anisotropically etching the remaining portion of the insulating material;

f) removing the spacers leaving the remaining portion of the first trench in the semiconductor layer with a width A″

that is greater than A′

; and

g) filling at least the second trench in the insulating material with a conductive material.

7. The method of claim 6 further comprising, before step b):

forming a first oxide layer on the sidewall and at the bottom of the trench; and

forming a nitride layer on top of the first oxide layer.

8. The method of claim 7, wherein d) further comprises:

forming a polysilicon layer with the predetermined thickness T1 on top of said nitride layer; and

anisotropically etching the polysilicon layer to form the spacers.

9. The method of claim 8 further comprising, after g):

etching back the conductive material to below a top surface of the insulating material in the trench to form a shield electrode;

forming an insulating layer on top of the conductive material in the trench;

removing the first oxide layer and the nitride layer exposed at the sidewall of the trench and at the top of the semiconductor layer;

forming an gate dielectric layer on the sidewall of the trench and at the top of the semiconductor layer; and

filling the remaining portion of the trench with another conductive material and etching back the conductive material to form a gate electrode.

10. The method of claim 6, wherein d) further includes:

forming a nitride layer with the predetermined thickness T1 on the sidewall of the remaining portion of the first trench, on top of the insulating material deposited in the trench and on top of the semiconductor layer; and

anisotropically etching the nitride layer to form the one or more spacers.

11. The method of claim 10, wherein d) further includes before said forming a nitride layer, forming a first oxide layer at least on the sidewall of the remaining portion of the first trench.

12. The method of claim 10, further comprising, before g):

forming a dielectric layer on the sidewall of the remaining portion of the first trench to serve as a gate dielectric;

wherein g) further comprises filling at least a portion of the first trench with the conductive material.

13. The method of claim 12 further comprising, after g):

etching back the conductive material.

14. The method of claim 12 further comprising:

filling an opening in the conductive material with an additional insulating material; and

etching back the additional insulating material and the conductive material.