Method for producing interconnect structures for integrated circuits

• US 8,252,659 B2
• Filed: 12/01/2009
• Issued: 08/28/2012
• Est. Priority Date: 12/02/2008
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Huyghebaert, Cedric, Vaes, Jan, Van Olmen, Jan
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/628,844
• Publication Number:
  US 20100133660A1
• Time in Patent Office: 1,001 Days
• Field of Search: 438/424, 438633-640, 438/667, 438/786, 257E21029-E21038, 257/252, 257/268, 257/269, 257/576, 257/579, 257/23.144, 257/145, 257/29.309
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The disclosure is equally related to devices obtainable by the method of the disclosure.

Claims

1. A method for producing a semiconductor device, comprising:

providing a semiconductor substrate, the semiconductor comprising one or more active components on a surface of the semiconductor substrate;

depositing a top layer of dielectric material on the surface of the substrate or on a dielectric layer present on the surface of the semiconductor substrate;

depositing a common chemical mechanical polishing stopping layer on the top layer;

etching one or more first openings through at least the top layer, filling the one or more first openings with a first conductive material, and performing a first chemical mechanical polishing to form first conductive structures, wherein the common chemical mechanical polishing stopping layer stops the first chemical mechanical polishing;

etching one or more second openings through at least the top layer, filling the one or more second openings with a second conductive material, and performing a second chemical mechanical polishing to form second conductive structures, wherein the common chemical mechanical polishing stopping layer stops the second chemical mechanical polishing.

2. The method of claim 1, wherein the top layer is a pre-metal dielectric stack deposited on the surface of the semiconductor substrate and wherein the one or more first openings filled with a first conductive material are contact vias for contacting the active components on a surface of the semiconductor substrate and the one or more second openings filled with a second conductive material are through substrate vias for connecting a sub-laying integrated circuit.

3. The method of claim 1, wherein the top layer is an intermetal dielectric layer deposited on a pre-metal dielectric stack or another intermetal dielectric layer on the surface of the semiconductor substrate, wherein the one or more first openings filled with a first conductive material are contact vias for contacting the active components on a surface of the semiconductor substrate and the one or more second openings filled with a second conductive material are through substrate vias for connecting a sub-laying integrated circuit.

4. The method of claim 2, further comprising:

providing the semiconductor substrate, wherein the semiconductor substrate further comprises a pre-metal dielectric stack;

thereafter

depositing the chemical mechanical polishing stopping layer;

thereafter

depositing photosensitive layers and patterning openings in the photosensitive layers to define contact vias in the pre-metal dielectric stack;

thereafter

etching the contact vias in the pre-metal dielectric stack and then stripping remaining photosensitive material;

thereafter

depositing a dielectric material and a barrier material onto sidewalls of the contact vias and then filling the contact vias with a first conductive material;

thereafter

removing an overburden of barrier material and first conductive material using chemical mechanical polishing to the chemical mechanical polishing stopping layer;

thereafter

depositing photosensitive layers and patterning openings in the photosensitive layers to define through substrate vias;

thereafter

etching the through substrate vias in the pre-metal dielectric stack and in a part of the semiconductor substrate and then stripping remaining photosensitive material;

thereafter

depositing a dielectric material and a barrier material onto the sidewalls of the through substrate vias and then filling the through substrate vias with a second conductive material; and

thereafter

removing the overburden of barrier material and second conductive material using chemical mechanical polishing.

5. The method of claim 4, wherein depositing a dielectric material and a barrier material onto sidewalls of the through substrate vias further comprises depositing a seed material onto sidewalls of the through substrate vias;

and wherein removing the overburden further comprises removing an overburden of seed material.

6. The method of claim 3, comprising:

providing the semiconductor substrate, wherein the semiconductor substrate comprises an at least partly completed back end of line stack comprising n-1 levels of vias and trenches embedded in an intermetal dielectric layer;

thereafter

depositing another intermetal dielectric layer to form level n of the back end of line stack;

depositing the chemical mechanical polishing stopping layer on top of the intermetal dielectric layer forming level n of the back end of line stack;

thereafter

depositing photosensitive layers on top of the chemical mechanical polishing stopping layer and patterning openings in the photosensitive layers to define trenches and/or vias within the intermetal dielectric layer forming level n of the back end of line stack;

thereafter

etching the trenches and/or vias within the patterned openings in the deposited intermetal dielectric layer forming level n of the back end of line stack and then stripping remaining photosensitive material;

thereafter

depositing at least one material selected from the group consisting of a dielectric material, a barrier material, and a seed material onto sidewalls of the trenches and/or vias;

thereafter

filling the trenches and/or vias with a first conductive material;

thereafter

removing an overburden of deposited material and first conductive material using chemical mechanical polishing;

thereafter

depositing photosensitive layers and patterning openings in the photosensitive layers to define through substrate vias;

thereafter

etching through substrate vias in the intermetal dielectric layer forming level n of the back end of line stack, wherein the through substrate vias further extend into the substrate, and then stripping remaining photosensitive material;

thereafter

depositing a dielectric material and a barrier material onto sidewalls of the through substrate vias and subsequently filling the through substrate vias with a second conductive material; and

thereafter

removing an overburden of dielectric material, barrier material, and second conductive material using chemical mechanical polishing.

7. The method of claim 6, wherein depositing a dielectric material and a barrier material onto sidewalls of the through substrate vias further comprises depositing a seed material onto sidewalls of the through substrate vias;

and wherein removing the overburden further comprises removing an overburden of seed material.

8. The method of claim 1, wherein the chemical mechanical polishing stopping layer is selected from the group consisting of a silicon carbon layer, a silicon nitride layer, a silicon oxycarbide layer, and a silicon oxynitride layer, and wherein the chemical mechanical polishing stopping layer is deposited using chemical vapor deposition.

9. The method of claim 1, wherein the substrate is a silicon substrate.