Methods of forming CMOS transistors with high conductivity gate electrodes
DCFirst Claim
1. A method of forming an insulated-gate transistor, comprising:
- forming a gate insulating layer on a substrate;
forming a metal buffer gate electrode layer on the gate insulating layer;
forming a dummy gate electrode layer on the buffer gate electrode layer, said dummy gate electrode layer and said buffer gate electrode layer comprising different materials;
patterning the dummy gate electrode layer and the buffer gate electrode layer in sequence to define a buffer gate electrode on the gate insulating layer and a dummy gate electrode on the buffer gate electrode;
forming electrically insulating spacers on sidewalls of the dummy gate electrode and on sidewalls of the buffer gate electrode;
covering the spacers and the dummy gate electrode with an electrically insulating mold layer;
removing an upper portion of the mold layer to expose an upper surface of the dummy gate electrode;
removing the dummy gate electrode from between the spacers by selectively etching back the dummy gate electrode using the mold layer and the spacers as an etching mask;
depositing a first metal layer onto an upper surface of the mold layer and onto inner sidewalls of the spacers and onto an upper surface of the buffer gate electrode;
filling a space between the inner sidewalls of the spacers by depositing a second metal layer onto a portion of the first metal layer extending between the inner sidewalls of the spacers to thereby define a metal gate electrode comprising a composite of the second metal layer, a portion of the first metal layer having a U-shaped cross-section and the buffer gate electrode.
1 Assignment
Litigations
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Accused Products
Abstract
Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.
97 Citations
15 Claims
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1. A method of forming an insulated-gate transistor, comprising:
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forming a gate insulating layer on a substrate; forming a metal buffer gate electrode layer on the gate insulating layer; forming a dummy gate electrode layer on the buffer gate electrode layer, said dummy gate electrode layer and said buffer gate electrode layer comprising different materials; patterning the dummy gate electrode layer and the buffer gate electrode layer in sequence to define a buffer gate electrode on the gate insulating layer and a dummy gate electrode on the buffer gate electrode; forming electrically insulating spacers on sidewalls of the dummy gate electrode and on sidewalls of the buffer gate electrode; covering the spacers and the dummy gate electrode with an electrically insulating mold layer; removing an upper portion of the mold layer to expose an upper surface of the dummy gate electrode; removing the dummy gate electrode from between the spacers by selectively etching back the dummy gate electrode using the mold layer and the spacers as an etching mask; depositing a first metal layer onto an upper surface of the mold layer and onto inner sidewalls of the spacers and onto an upper surface of the buffer gate electrode; filling a space between the inner sidewalls of the spacers by depositing a second metal layer onto a portion of the first metal layer extending between the inner sidewalls of the spacers to thereby define a metal gate electrode comprising a composite of the second metal layer, a portion of the first metal layer having a U-shaped cross-section and the buffer gate electrode. - View Dependent Claims (2, 3, 4, 5)
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6. A method of forming an integrated circuit device, comprising:
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forming a gate insulating layer on a substrate; forming a first metal gate electrode layer on the gate insulating layer; forming a dummy gate electrode layer on the first metal gate electrode layer, said dummy gate electrode layer and said first metal gate electrode layer comprising different materials; patterning the dummy gate electrode layer and the first metal gate electrode layer in sequence to define a dummy gate electrode on the patterned first metal gate electrode layer; forming electrically insulating spacers on sidewalls of the dummy gate electrode and on sidewalls of the patterned first metal gate electrode layer; removing the dummy gate electrode from between the spacers by selectively etching back the dummy gate electrode using the spacers as an etching mask; depositing a second metal gate electrode layer onto inner sidewalls of the spacers and onto an upper surface of the patterned first metal gate electrode layer; depositing a third metal gate electrode layer onto the second metal gate electrode layer to thereby fill a space between the inner sidewalls of the spacers, said second and third metal gate electrode layers comprising different materials; planarizing the third metal gate electrode layer and the second metal gate electrode layer to thereby define a composite metal gate electrode of a PMOS transistor between the inner sidewalls of the spacers, said composite metal gate electrode comprising a portion of the third metal gate electrode layer, a portion of the second metal gate electrode layer having a U-shaped cross-section and the patterned first metal gate electrode layer. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification