MOS device with varying trench depth

• US 8,253,192 B2
• Filed: 04/15/2011
• Issued: 08/28/2012
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/088,275
• Publication Number:
  US 20110210390A1
• Time in Patent Office: 501 Days
• Field of Search: 257/330, 257/331, 257/332
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.

Claims

1. A semiconductor device comprising:

a drain region comprising an epitaxial layer;

a body disposed in the epitaxial layer;

a source embedded in the body;

a gate trench extending into the epitaxial layer;

a gate disposed in the gate trench;

an active region contact trench extending through the source, the active region contact trench having a first depth associated with a first region that is in proximity to a bottom portion of the body and a second depth associated with a second region that is in proximity to a bottom portion of the source, the first depth being substantially different from the second depth; and

an active region contact electrode disposed within the active region contact trench; and

a Schottky barrier controlling layer formed in the first region in the active region contact trench;

wherein;

the first depth extends from an oxide layer to the first region; and

the second depth extends from an oxide layer to the second region.

2. The semiconductor device of claim 1, wherein a Schottky contact is formed in the first region.

3. The semiconductor device of claim 1, wherein a Schottky contact is formed in the first region by the active region contact electrode and the drain.

4. The semiconductor device of claim 1, wherein a Schottky contact is formed in the first region by the active region contact electrode and the drain, and the Schottky barrier controlling layer is formed in the epitaxial layer below the Schottky contact.

5. The semiconductor device of claim 1, wherein a Schottky contact is formed in the first region, and the semiconductor device further comprises an anti-punch through implant on a side wall of the first region of the active region contact trench.

6. The semiconductor device of claim 5, wherein the anti-punch through implant is formed by a heavily doped region.

7. The semiconductor device of claim 5, wherein a body contact is formed in the second region by the active region contact electrode and the heavily doped region.

8. The semiconductor device of claim 1, wherein a Schottky contact is formed in the first region and a body contact is formed in the second region.

9. The semiconductor device of claim 8, wherein the body contact is formed in the second region by the active region contact electrode and a heavily doped region.

10. The semiconductor device of claim 1, wherein the semiconductor device includes a striped cell device.

11. The semiconductor device of claim 1, wherein the semiconductor device includes a closed cell device.

12. The semiconductor device of claim 1, wherein the semiconductor device includes a rectangular closed cell device having a width and a length, and the active region contact trench forms a first contact trench depth and a second contact trench depth along a length-wise cross section.

13. The semiconductor device of claim 1, wherein the semiconductor device includes a closed cell device having a width and a length, and the active region contact trench forms a first contact trench depth and a second contact trench depth along both a length-wise cross section and a width-wise cross section.

14. The semiconductor device of claim 1, wherein an area ratio of the first region and the second region is controlled to meet both an unclamped inductive switching (UIS) recovery requirement and a diode recovery requirement.

15. The semiconductor device of claim 1, wherein the semiconductor device is included in a multi-cell device that includes at least one cell that has a corresponding active region contact trench that is uniform in depth.