Semiconductor device including a magnetic sensor chip

• US 8,253,210 B2
• Filed: 04/30/2009
• Issued: 08/28/2012
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Theuss, Horst, Elian, Klaus
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US12/433,531
• Publication Number:
  US 20100276769A1
• Time in Patent Office: 1,216 Days
• Field of Search: 257/414, 257421-427, 257/E29.323, 438/3, 360324-326, 365157-158
• US Class Current: 257/421
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G01R 33/093 using multilayer structures, e.g. giant magnetoresistance sensors thin magnetic films H01F10/00
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/21 of an individual HDI interconnect
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H10B 61/00 : Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 59/00 : Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

A semiconductor device includes a magnetic sensor chip, an electrically conducting layer wafer-level patterned in contact with the magnetic sensor chip, encapsulation material disposed on the magnetic sensor chip, and an array of external contact elements electrically coupled with the magnetic sensor chip through the electrically conducting layer.

Claims

1. A semiconductor device comprising:

a magnetic sensor chip;

an electrically conducting layer wafer-level patterned in contact with the magnetic sensor chip;

encapsulation material disposed on the magnetic sensor chip;

an array of external contact elements electrically coupled with the magnetic sensor chip through the electrically conducting layer;

wherein the magnetic sensor chip comprises a semiconductor chip and the encapsulation material comprises a magnetic encapsulation material deposited over the semiconductor chip opposite the electrically conducting layer; and

a non-magnetic layer between the semiconductor chip and the magnetic encapsulation material.

2. The semiconductor device of claim 1, wherein the non-magnetic layer comprises at least one major surface structured and so configured to shape magnetic field lines passing through the semiconductor chip.

13. A method of manufacturing the semiconductor device of claim 1, the method comprising:

placing multiple magnetic sensor chips on a carrier, each of the multiple magnetic sensor chips comprising contact elements facing the carrier;

applying encapsulation material over the multiple magnetic sensor chips and the carrier and forming an encapsulated work piece; and

singulating the multiple magnetic sensor chips from the encapsulated work piece.

14. The method of claim 13, further comprising:

separating the encapsulated work piece from the carrier.

15. The method of claim 14, further comprising:

structuring a major surface of the non-magnetic layer opposite the multiple chips, the structuring configured to shape magnetic field lines that pass through each chip; and

applying magnetic encapsulation material over the non-magnetic layer.

16. The method of claim 15, further comprising:

depositing a dielectric layer over the electrically conducting layer, selectively opening the dielectric layer, and patterning an array of external contacts in contact with the electrically conducting layer.

17. The method of claim 13, wherein each of the multiple magnetic sensor chips comprises a semiconductor chip and the encapsulation material comprises magnetic encapsulation material.

18. The method of claim 13, wherein singulating the multiple magnetic sensor chips from the encapsulated work piece comprises one of sawing, cutting, laser irradiating, and etching individual magnetic sensor chips from the encapsulated work piece.

3. A semiconductor device comprising:

a chip comprising contact elements on a first main face of the chip;

an electrically conducting layer wafer-level patterned in contact with the contact elements of the chip;

magnetic encapsulation material disposed on the chip; and

an array of external contact elements coupled to the electrically conducting layer and electrically communicating with the contact elements of the chip,

wherein the array of external contact elements is patterned into a dielectric layer disposed over the electrically conducting layer.

4. The semiconductor device of claim 3, further comprising:

a solder ball connected to a pad of at least one of the array of external contact elements.

9. The semiconductor device of claim 3, wherein the chip comprises one of a Hall sensor, a magneto-resistive element, and a giant magnetic resistor.

19. A method of manufacturing the semiconductor device of claim 3, the method comprising:

placing multiple chips on a carrier, each of the multiple chips comprising contact elements facing the carrier;

applying magnetic encapsulation material over the multiple chips and the carrier and forming an encapsulated work piece; and

singulating the multiple chips from the encapsulated work piece.

20. The method of claim 19, further comprising:

depositing a non-magnetic layer over the multiple chips opposite the contact elements;

structuring a major surface of the non-magnetic layer opposite the multiple chips, the structuring configured to shape magnetic field lines that pass through each chip; and

applying magnetic encapsulation material over the non-magnetic layer.

21. The method of claim 19, wherein applying magnetic encapsulation material comprises applying a polymer matrix containing a distribution of permanent magnetic particles.

22. The method of claim 19, further comprising:

separating the encapsulated work piece from the carrier;

patterning an electrically conducting layer onto the contact elements of the multiple chips; and

depositing a dielectric layer over the electrically conducting layer, selectively opening the dielectric layer, and patterning an array of external contacts in contact with the electrically conducting layer.

5. A semiconductor device comprising:

a chip comprising contact elements on a first main face of the chip;

an electrically conducting layer wafer-level patterned in contact with the contact elements of the chip;

magnetic encapsulation material disposed on the chip; and

an array of external contact elements coupled to the electrically conducting layer and electrically communicating with the contact elements of the chip,

wherein the magnetic encapsulation material comprises a polymer matrix comprising permanent magnetic particles distributed within the polymer matrix.

6. The semiconductor device of claim 5, wherein a first portion of the magnetic encapsulation material is selectively demagnetized and a second portion of the magnetic encapsulation material is selectively magnetized.

7. A semiconductor device comprising:

a chip comprising contact elements on a first main face of the chip;

an electrically conducting layer wafer-level patterned in contact with the contact elements of the chip;

magnetic encapsulation material disposed on the chip;

an array of external contact elements coupled to the electrically conducting layer and electrically communicating with the contact elements of the chip;

a non-magnetic layer between the chip and the magnetic encapsulation material.

8. The semiconductor device of claim 7, wherein the non-magnetic layer comprises at least one surface structured and configured to shape magnetic field lines passing through the chip.

10. A semiconductor device comprising:

a chip comprising contact elements on a first face; and

magnetic encapsulation material wafer-level deposited over a second face of the chip opposite the first face, wherein singulation of the semiconductor device from a wafer provides a chip-sized package with the magnetic encapsulation material embedding sides of the chip.

11. The semiconductor device of claim 10, further comprising:

a non-magnetic layer disposed on at least a portion of the second face of the chip, the non-magnetic layer comprising a first surface in contact with the second face of the chip and a second surface opposite the first surface, the second surface of the non-magnetic layer comprising a non-linear surface configured to shape a magnetic field lines relative to a sensor surface of the chip.

12. The semiconductor device of claim 10, further comprising:

a through-silicon via formed between the first and second faces of the chip and an electrical pathway established in the through-silicon via extending between each contact element and the second face of the chip.