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Method and apparatus of providing 2-stage ESD protection for high-speed interfaces

  • US 8,254,071 B2
  • Filed: 07/25/2008
  • Issued: 08/28/2012
  • Est. Priority Date: 08/14/2007
  • Status: Active Grant
First Claim
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1. An electrostatic discharge (ESD) protection device that protects another separate protected device from an ESD event pulse by transmitting the ESD event pulse to ground and that passes a signal to the separate protected device, the ESD protection device comprising:

  • an integrated semiconductor provided in a first package adapted to be mounted on a printed circuit board, the integrated semiconductor including;

    an input pad that receives the signal and the ESD event pulse;

    an output pad adapted to pass the signal from the integrated semiconductor to a device under protection provided in a second package different from the first package; and

    an electrostatic discharge circuit connected between the input pad and the output pad, wherein the electrostatic discharge circuit passes the signal to the output pad and dissipates the ESD event pulse by providing a path to the ground for the ESD event pulse, the electrostatic discharge circuit comprising;

    a first stage that contains a first ESD clamp device that provides an electrostatic discharge path to the ground for the ESD event pulse;

    a second stage that contains a second ESD clamp device that provides another electrostatic discharge path to the ground for the ESD event pulse, such that the first stage clamps more energy from the ESD event pulse than the second stage; and

    a series coupling element that couples the first stage to the second stage, so that during the ESD event, the first stage turns on independently of the second stagewherein the separate protected device is mounted on the printed circuit board and the integrated semiconductor is adapted to be mounted on the printed circuit board such that the integrated semiconductor is disposed in series with the separate protected device, andwherein a transmission line impedance of the integrated semiconductor is tuned using bond wires of the first package.

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