Flow-control in a switch fabric

• US 8,254,255 B2
• Filed: 12/29/2008
• Issued: 08/28/2012
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Thomas, Philip A.
• Primary Examiner(s): CHAN, SAI MING
• Application Number:
  US12/345,490
• Publication Number:
  US 20100165843A1
• Time in Patent Office: 1,338 Days
• Field of Search: 370/235, 370/230
• US Class Current: 370/230
• CPC Class Codes: H04L 12/50 Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

In some embodiments, an apparatus includes a module within a first stage of a switch fabric, a module within a second stage of the switch fabric, and a module within a third stage of the switch fabric. The module within the first stage is configured to send data to the module within the second stage. The module within the second stage is configured to send data to the module within the third stage. The module within the second stage is configured to send a first suspension indicator to the module within the third stage. The module within the third stage is configured to send a second suspension indicator to the module within the first stage in response to the first suspension indicator. The module within the first stage is configured to stop sending data to the module within the second stage in response to the second suspension indicator.

Claims

1. An apparatus, comprising:

a module within a first stage of a switch fabric;

a module within a second stage of the switch fabric, the module within the second stage including a queue within a memory to buffer data, the module within the first stage to send data to the module within the second stage; and

a module within a third stage of the switch fabric, the module within the third stage being within a same chip package as the module within the first stage, the module within the second stage to send data to the module within the third stage,

the module within the second stage to send a first suspension indicator to the module within the third stage in response to an amount of data within the queue exceeding a threshold, the module within the third stage to send a second suspension indicator to the module within the first stage in response to the first suspension indicator, the module within the first stage to stop sending data to the module within the second stage in response to the second suspension indicator.

2. The apparatus of claim 1, wherein the module within the third stage is to send a third suspension indicator to the module within the first stage, the module within the first stage to send a fourth suspension indicator to the module within the second stage in response to the third suspension indicator, the module within the second stage to stop sending data to the module within the third stage in response to the fourth suspension indicator.

3. The apparatus of claim 1, wherein the module within the second stage is within a first chip package, the module within the first stage and the module within the third stage are within a second chip package different from the first chip package.

4. The apparatus of claim 1, further comprising:

a module within a fourth stage of the switch fabric to send data to the module within the first stage; and

a module within a fifth stage of the switch fabric to receive data from the module within the third stage,

the module within the first stage to send a third suspension indicator to the module within the third stage, the module within the third stage to send a fourth suspension indicator to the module within the fifth stage in response to the third suspension indicator, the module within the fifth stage to send a fifth suspension indicator to the module within the fourth stage, the module within the fourth stage to stop sending data to the module within the first stage in response to the fifth suspension indicator.

5. The apparatus of claim 4, wherein the module within the fourth stage and the module within the fifth stage are within a same chip package.

6. The apparatus of claim 1, wherein the module within the second stage is to send the first suspension indicator to the module within the third stage when the module within the second stage is unable to receive additional data from the module within the first stage.

7. The apparatus of claim 1, wherein the module within the second stage is to send data to the module within the third stage via a data connection, the module within the second stage is to send the second suspension indicator to the module within the third stage via the data connection.

8. The apparatus of claim 1, wherein the module within the second stage is to send a first actuation indicator to the module within the third stage, the module within the third stage is to send a second actuation indicator to the module within the first stage in response to the first actuation indicator, the module within the first stage is to send data from the module within the first stage to the module within the second stage in response to the second actuation indicator.

9. A method, comprising:

sending data from a module within a first stage of a switch fabric to a module within a second stage of the switch fabric;

sending a first suspension indicator from the module within the second stage to a module within a third stage of the switch fabric in response to an amount of data in a buffer of the module within the second stage exceeding a threshold; and

sending a second suspension indicator from the module within the third stage to the module within the first stage in response to the first suspension indicator, the module within the first stage to stop sending data to the module within the second stage in response to the second suspension indicator, the module within the third stage being within a same chip package as the module within the first stage.

10. The method of claim 9, further comprising:

sending a first actuation indicator from the module within the second stage to the module within the third stage;

sending a second actuation indicator from the module within the third stage to the module within the first stage in response to the first actuation indicator, the module within the first stage to resume sending data to the module within the second stage in response to the second actuation indicator.

11. A non-transitory processor-readable medium storing code representing instructions to cause a processor to perform a process, the code comprising code to:

receive data from a module within a first stage of a switch fabric;

buffer the data in a queue within a memory;

forward the buffered data to a module within a second stage of the switch fabric, the module within the second stage being within a same chip package as the module within the first stage; and

send a suspension indicator to the module within the second stage when an amount of data within the queue exceeds a threshold, the suspension indicator to stop the module within the first stage from sending data.

12. The non-transitory processor-readable medium of claim 11, the code further comprising code to:

send an actuation indicator to the module within the second stage, the actuation indicator to request data from the module within the first stage.

13. An apparatus, comprising:

a module within a first stage of a switch fabric;

a module within a second stage of the switch fabric;

a module within a third stage of the switch fabric, the module within the third stage being within a same chip package as the module within the first stage;

a first unidirectional data path, the first unidirectional data path to facilitate data transfer from the module within the first stage to the module within the second stage;

a second unidirectional data path, the second unidirectional data path to facilitate data transfer from the module within the second stage to the module within the third stage; and

a bidirectional data path to facilitate transfer of a flow-control indicator from the module within the third stage to the module within the first stage, the module within the third stage to send the flow-control indicator to the module within the first stage when the module within the second stage is unable to receive additional data from the module within the first stage.

14. The apparatus of claim 13, wherein the flow-control indicator is to cause the module within the first stage to stop sending data to the module within the second stage.

15. The apparatus of claim 13, wherein the flow-control indicator is to cause the module within the first stage to send data to the module within the second stage.

16. The apparatus of claim 13, wherein the module within the second stage includes a buffer, the module within the second stage to send a flow-control indicator to the module within the third stage in response to an amount of data in the buffer exceeding a threshold, the flow-control indicator from the module within the second stage is to cause the module within the third stage to send the flow-control indicator from the module within the third stage to the module within the first stage.

17. The apparatus of claim 13, wherein the module within the second stage is within a chip package distinct from the chip packaging containing the module within the first stage and the module within the third stage.

18. The apparatus of claim 13, wherein the module within the second stage is to send a flow-control indicator to the module within the third stage via the second unidirectional data path.