Method and apparatus for two dimensional image processing

• US 8,254,728 B2
• Filed: 07/09/2009
• Issued: 08/28/2012
• Est. Priority Date: 02/14/2002
• Status: Active Grant

• Current Assignee: Gemalto SA (Thales SA)
• Original Assignee: 3M Cogent Incorporated (Thales SA)
• Inventors: Hsieh, Ming, Xue, Huansheng, Wang, Jing, Lu, Chunyu
• Primary Examiner(s): Alavi, Amir
• Application Number:
  US12/500,554
• Publication Number:
  US 20090268988A1
• Time in Patent Office: 1,146 Days
• Field of Search: 382168-169, 382/228, 382/254, 382258-259, 382271-272, 382303-305, 709/203, 709/224, 709/226, 709/229, 709/250, 345/502, 345/505, 345/546, 370/352, 370/375, 370/428, 370/458, 370/485, 358/455, 358/460, 358/522
• US Class Current: 382/305
• CPC Class Codes: G06F 17/18 for evaluating statistical data , e.g. average values, frequency distributions, probability functions, regression analysis forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04
• CPC Class Codes: G06T 1/60 Memory management

Abstract

In one embodiment, the present invention is a system for organizing data flow for two dimensional digital image processing. The system includes a memory access module for accessing an external memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Claims

1. A system for organizing data flow for two-dimensional image processing comprising:

an address engine for generating addresses for reading image data from and writing image data to an external memory, the address engine comprising;

a DMA unit for interfacing with the external memory, and

a data flow organizer module for re-ordering the image data read from the external memory and generating data flows for the image data to be processed; and

a data processing module for processing the image data read from the external memory, wherein

the DMA unit comprises;

a plurality of first read address generation units for generating read addresses for reading the image data from the external memory, and

at least one first write address generation units for generating write addresses for writing the image data to the external memory, and wherein the data flow organizer module comprises;

a cache memory divided into a plurality of virtual memories,

a lookup table for storing function data,

a plurality of second read address generation units for generating read addresses for reading data from the cache memory, each of the second read address generation units corresponding to a respective one of the plurality of virtual memories,

a plurality of second write address generation units for generating write addresses for writing data to the cache memory, each of the second write address generation units corresponding to a respective one of the plurality of virtual memories,

a control and synchronization circuit for ensuring that the data is in the cache memory and push the data to the data processing module, when need, and

a plurality of pointer registers for ensuring that reading each memory cell in the cache memory is performed later than writing to said memory cell.

2. The system of claim 1, further comprising a plurality of FIFOs to regulate data transfers.

3. The system of claim 1, wherein the data processing module is a RISC machine.

4. The system of claim 1, wherein the data processing module includes mode register for controlling the type of data processing to be performed on the image data.

5. The system of claim 1, wherein the plurality of first read address generation units and first write address generation units perform block scanning.

6. The system of claim 1, wherein addresses for function data stored in the lookup table is an angle of one or more image attributes and values stored in the addresses are SIN or Tan of respective addresses.

7. The system of claim 1, wherein each of the plurality of virtual memories corresponds to a respective area and each area includes a first programmable parameter to determine an offset of each area, and a second and a third programmable parameter to determine a size of each area.

8. The system of claim 7, wherein each of the respective areas stores a different type of data, which has a logical relationship in every corresponding pixel of the image.

9. The system of claim 8, wherein a first area stores red components of a color image, a second area stores green components of a color image, and a third area stores blue components of a color image.

10. The system of claim 1, wherein the cache memory is a dual-port RAM.

11. The system of claim 1, wherein the cache memory is a single-port RAM.

12. The system of claim 1, further comprising a plurality of control registers for controlling a scan mode of the image.

13. The system of claim 1, wherein the data processing module comprises:

a plurality of registers for controlling input data flow and output data flow;

a computation unit coupled to some of the a plurality of registers for performing arithmetic and logic calculations

an instruction/data memory coupled to the computation unit for storing instructions and data;

an execution controller for controlling instruction flow and accessing the instruction/data memory; and

a pipeline output interface for controlling flow of the output data.

14. The system of claim 1, wherein the image data comprises one of the group consisting of fingerprint image data, facial image data, eye iris image data, and retina image data.