Scalable distributed memory and I/O multiprocessor system
First Claim
1. A multiprocessor system comprising:
- at least one processing module including at least one processor, a memory, and a memory controller; and
an interconnect network for coupling to the at least one processing module, the interconnect network comprising;
at least two bridges to send and receive transactions from at least one input/output module and the processing module; and
at least two crossbar switches to route the transactions over a bus between the at least two bridges.
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Abstract
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
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Citations
20 Claims
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1. A multiprocessor system comprising:
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at least one processing module including at least one processor, a memory, and a memory controller; and an interconnect network for coupling to the at least one processing module, the interconnect network comprising; at least two bridges to send and receive transactions from at least one input/output module and the processing module; and at least two crossbar switches to route the transactions over a bus between the at least two bridges. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multiprocessor system comprising:
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at least one processing module including at least one processor, a memory, and a memory controller; at least one input/output module; one or more buses to communicatively couple the at least one processing module and the at least one input/output module; and at least one interconnect component coupled to each one of the processing module and the input/output module, the interconnect component to support the protocol of the one or more buses between the processing module and the input/output module. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An integrated circuit comprising:
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a crossbar router; a bridge communicatively coupled to the crossbar router, the bridge to packetize transactions between a processing module and an input/output (I/O) module in a format that is compatible with the crossbar router; and at least one Direct Memory Access (DMA) engine coupled to the crossbar router. - View Dependent Claims (18, 19, 20)
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Specification