Interface, memory system, and access control method
First Claim
Patent Images
1. An interface, comprising:
- a controller that divides a burst access command, which comprises an external block address and an initial address to be incremented, into a plurality of command cycles, and supplies the plurality of command cycles to a storage device including a plurality of blocks; and
a block address converter that outputs an address at a first command cycle of the plurality of command cycles, the outputted address being obtained by shifting at least one bit of the external block address input in response to the burst access command,wherein the outputted address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at one of the plurality of command cycles other than the first command cycle.
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Abstract
An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.
15 Citations
9 Claims
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1. An interface, comprising:
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a controller that divides a burst access command, which comprises an external block address and an initial address to be incremented, into a plurality of command cycles, and supplies the plurality of command cycles to a storage device including a plurality of blocks; and a block address converter that outputs an address at a first command cycle of the plurality of command cycles, the outputted address being obtained by shifting at least one bit of the external block address input in response to the burst access command, wherein the outputted address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at one of the plurality of command cycles other than the first command cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory system, comprising:
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a storage device which includes a plurality of blocks; a controller that divides a burst access command, which comprises an external block address and an initial address to be incremented, into a plurality of command cycles, and supplies the plurality of command cycles to the storage device; and a block address converter that outputs an address at a first command cycle of the plurality of command cycles, the outputted address being obtained by shifting at least one bit of the external block address input in response to the burst access command, wherein the outputted address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at one of the plurality of command cycles other than the first command cycle.
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9. An access control method, comprising:
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dividing a burst access command, which comprises an external block address and an initial address to be incremented, into a plurality of command cycles; supplying the command cycles to a storage device including a plurality of blocks; and supplying an address to the storage device at a first command cycle of the plurality of command cycles, the address being obtained by shifting at least one bit of the external block address input in response to the burst access command, and supplying the external block address to the storage device at one of the plurality of command cycles other than the first command cycle.
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Specification