Dynamically replicated memory

• US 8,255,742 B2
• Filed: 11/18/2009
• Issued: 08/28/2012
• Est. Priority Date: 11/18/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Ipek, Engin, Condit, Jeremy P., Nightingale, Edmund B., Burger, Douglas C., Moscibroda, Thomas
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US12/621,419
• Publication Number:
  US 20110119538A1
• Time in Patent Office: 1,014 Days
• Field of Search: 714/6.13, 714/6.32, 714/25, 714/30, 714/42, 714/710, 714/718, 365/200, 365/201
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.

Claims

1. A computer implemented method of reclaiming failed memory pages, the method comprising:

dynamically detecting a plurality of failed memory pages within a memory space, each failed memory page having at least one failed location;

dynamically pairing a first failed memory page of the plurality of failed memory pages with a second failed memory page of the plurality of failed memory pages, wherein the first failed memory page and the second failed memory page are compatible failed memory pages containing failed memory blocks located in different positions of each of the first and second failed memory pages; and

responsive to the pairing, creating a useable memory page from the paired first and second failed memory pages that contains no failed memory blocks at each location.

2. The method of claim 1, further comprising:

writing a plurality of data to the plurality of memory pages having at least one failed location within the memory space prior to discovering the at least one failed location in the plurality of memory pages; and

writing the plurality of data to useable memory pages in the memory space after discovering the at least one failed location in the plurality of memory pages.

3. The method of claim 1, wherein the pairing further comprises:

creating a page table for storing a mapping of virtual address spaces to physical address spaces; and

creating a real table for storing a mapping of physical address spaces to real address spaces.

4. The method of claim 3, wherein the mapping of physical address spaces to real address spaces comprises:

mapping a physical address location to a real address location in the real address space, the real address space comprising;

a pristine memory page containing no failed memory blocks or a a pair of memory pages comprising at least two compatible failed memory pages.

5. The method of claim 3, wherein a first translation lookaside buffer (TLB) data array is extended to accommodate a mapping of a virtual address location to one of the real address locations or a mapping of the virtual address location to at least two of the real address locations.

6. The method of claim 1, wherein the memory space comprises phase change memory.

7. A system comprising:

one or more processors; and

memory storing instructions that when executed by the one or more processors configures the one or more processors to perform acts comprising;

dynamically detecting a plurality of failed memory pages within a memory space, each failed memory page having at least one failed location;

dynamically pairing a first failed memory page of the plurality of failed memory pages with a second failed memory page of the plurality of failed memory pages, wherein the first failed memory page and the second failed memory page are compatible failed memory pages containing failed memory blocks located in different positions of each of the first and second failed memory pages; and

responsive to the pairing, creating a useable memory page from the paired first and second failed memory pages that contains no failed memory blocks at each location.

8. The system of claim 7, the acts further comprising:

writing a plurality of data to the plurality of memory pages having at least one failed location within the memory space prior to discovering the at least one failed location in the plurality of memory pages; and

writing the plurality of data to useable memory pages in the memory space after discovering the at least one failed location in the plurality of memory pages.

9. The system of claim 7, wherein the pairing further comprises:

creating a page table for storing a mapping of virtual address spaces to physical address spaces; and

creating a real table for storing a mapping of physical address spaces to real address spaces.

10. The system of claim 9, wherein the mapping of physical address spaces to real address spaces comprises:

mapping a physical address location to a real address location in the real address space, the real address space comprising;

a pristine memory page containing no failed memory blocks or a pair of memory pages comprising at least two compatible failed memory pages.

11. The system of claim 9, wherein a first translation lookaside buffer (TLB) data array is extended to accommodate a mapping of a virtual address location to one of the real address locations or a mapping of the virtual address location to at least two of the real address locations.

12. The system of claim 7, wherein the memory space comprises phase change memory.

13. One or more computer-readable storage media, storing computer-executable instructions that, when executed, configure a processor to perform acts for detecting and reliably recording memory faults, the acts comprising:

dynamically detecting a plurality of failed memory pages within a memory space, each failed memory page having at least one failed location;

dynamically pairing a first failed memory page of the plurality of failed memory pages with a second failed memory page of the plurality of failed memory, wherein the first failed memory page and the second failed memory page are compatible failed memory pages containing failed memory blocks located in different positions of each of the first and second failed memory pages; and

responsive to the pairing, creating a useable memory page from the paired first and second failed memory pages that contains no failed memory blocks at each location.

14. The one or more computer-readable storage media of claim 13, the acts further comprising:

writing a plurality of data to the plurality of memory pages having at least one failed location within the memory space prior to discovering the at least one failed location in the plurality of memory pages; and

writing the plurality of data to useable memory pages in the memory space after discovering the at least one failed location in the plurality of memory pages.

15. The one or more computer-readable storage media of claim 13, wherein the pairing further comprises:

creating a page table for storing a mapping of virtual address spaces to physical address spaces; and

creating a real table for storing a mapping of physical address spaces to real address spaces.

16. The one or more computer-readable storage media of claim 15, wherein the mapping of physical address spaces to real address spaces comprises:

mapping a physical address location to a real address location in the real address space, the real address space comprising;

a pristine memory page containing no failed memory blocks or a pair of memory pages comprising at least two compatible failed memory pages.

17. The one or more computer-readable storage media of claim 15, wherein a first translation lookaside buffer (TLB) data array is extended to accommodate a mapping of a virtual address location to one of the real address locations or a mapping of the virtual address location to at least two of the real address locations.

18. The one or more computer-readable storage media of claim 13, wherein the memory space comprises phase change memory.