Hardware-error tolerant computing

• US 8,255,745 B2
• Filed: 01/08/2009
• Issued: 08/28/2012
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Hillis, W. Daniel, Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T, Wood, Lowell L. Jr.
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US12/319,696
• Publication Number:
  US 20090132853A1
• Time in Patent Office: 1,328 Days
• Field of Search: 714 15- 17, 713/322
• US Class Current: 714/19
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

Claims

1. A computing system comprising:

a processor subsystem having an adjustable physical operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem;

a recovery circuit operable to rollback an execution of the sequence of instructions to a checkpoint in response to the detected operating-parameter-caused error; and

a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error, to substantially minimize a time to complete an execution of the sequence of instructions by adjusting the adjustable physical operating parameter including adjusting a processor subsystem voltage in response to the error-tolerant performance criterion, wherein the error-tolerant performance criterion corresponds in substantial conformity to 0=(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

adjustable physical operating parameter).

2. The computing system of claim 1, wherein the monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem is configured for detecting an incidence of a computational error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

3. The computing system of claim 1, wherein the monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem is configured for detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

4. The computing system of claim 1, wherein the monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem is implemented in at least one of hardware, software, firmware, and/or a microengine for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

5. The computing system of claim 1, wherein the monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem is implemented in a dynamic implementation verification architecture (DIVA).

6. The computing system of claim 1, wherein the monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem employs a TEATime execution checker.

7. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is implemented in at least one of hardware, software, firmware, and/or a microengine.

8. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust a frequency of a timing signal employed by the processor subsystem based upon an error-tolerant performance criterion.

9. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust a processor clock based upon an error-tolerant performance criterion.

10. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust a processor clock frequency to substantially minimize a time to complete an execution of the sequence of instructions.

11. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust a processor clock frequency to substantially minimize an expected time to successfully complete an execution of the sequence of instructions while at least one other adjustable physical operating parameter remains substantially constant.

12. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust the adjustable physical operating parameter based upon an empirically-based error-tolerant performance map.

13. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust the adjustable physical operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error.

14. The computing system of claim 1, wherein the controller module includes an error recovery circuit operable to restore an execution of the sequence of program instructions to a checkpoint based upon the detected operating-parameter-caused error.

15. The computing system of claim 1, wherein the adjustable physical operating parameter includes:

an adjustable electrical operating parameter.

16. The computing system of claim 1, wherein the adjustable physical operating parameter includes:

an adjustable thermal operating parameter.

17. The computing system of claim 1, wherein the error-tolerant performance criterion is dynamically-derived.

18. The computing system of claim 17, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant dynamically-derived performance criterion is configured to adjust the adjustable physical operating parameter based upon an error-tolerant dynamically-derived performance criterion having an objective to substantially minimize an expected time to successfully complete an execution of the sequence of instruction.

19. The computing system of claim 1, wherein the control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion is configured to adjust the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table.

20. The computing system of claim 19, wherein the control circuit for adjusting the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table is configured to adjust the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table and having an objective of substantially minimizing a time to complete an execution of the sequence of instruction.

21. A method implemented in a computerized system, the method comprising:

detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter;

rollbacking the execution of the instruction of the sequence to a checkpoint in response to the detected incidence of the operating-parameter-caused error; and

changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error, to substantially minimize a time required to successfully complete an execution of the sequence of instructions by adjusting the adjustable physical operating parameter including adjusting a processor subsystem voltage in response to the error-tolerant performance criterion, wherein the error-tolerant performance criterion corresponds in substantial conformity to 0=(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

adjustable physical operating parameter).

22. The method of claim 21, wherein the method further comprises:

detecting an incidence of a setup/hold violation corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter.

23. The method of claim 21, wherein the method further comprises:

detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of a sequence of instructions by the processor subsystem having the adjustable physical operating parameter.

24. The method of claim 21, wherein the method further comprises:

detecting an incidence of at least one of a single incidence, an incidence frequency, an incidence occurrence rate, an incidence tempo, an incidence pattern, or an incidence prevalence of a processor-operating-parameter-caused error corresponding to the execution of the instruction of the sequence of instructions by the processor subsystem having the adjustable physical operating parameter.

25. The method of claim 21, wherein the error-tolerant performance criterion is dynamically-derived.

26. The method of claim 21, wherein the changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion includes:

determining that changing the adjustable processor physical operating parameter is at least substantially likely to decrease a time to complete an execution of the sequence of instructions by the processor.

27. The method of claim 21, wherein the adjustable processor physical operating parameter includes:

an adjustable electrical operating parameter.

28. The method of claim 21, wherein the adjustable processor physical operating parameter includes:

an adjustable thermal operating parameter.

29. A device comprising:

means for detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable physical operating parameter;

means for changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error, to substantially minimize a time required to successfully complete an execution of the sequence of instructions by adjusting the adjustable physical operating parameter including adjusting a processor subsystem voltage in response to the error-tolerant performance criterion, wherein the error-tolerant performance criterion corresponds in substantial conformity to 0=(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

adjustable physical operating parameter); and

means for restoring an execution of the sequence of program instructions to a checkpoint based upon the detected processor-operating-parameter-caused error in response to the detected incidence of the operating-parameter-caused error.

30. A method implemented in a computerized system that includes a processor system having an adjustable physical operating parameter, the method comprising:

detecting an incidence of a processor error corresponding to an execution by the processor system of an instruction of a sequence of instructions;

rollbacking the execution of the instruction of the sequence to a checkpoint in response to the detected incidence of the operating-parameter-caused error; and

changing the adjustable processor physical operating parameter in response to the detected incidence of error and in response to an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error, to substantially minimize a time required to successfully complete an execution of the sequence of instructions by adjusting the adjustable physical operating parameter, wherein the error-tolerant performance criterion corresponds in substantial conformity to 0=(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

adjustable physical operating parameter).