Adaptive memory scrub rate

• US 8,255,772 B1
• Filed: 06/18/2008
• Issued: 08/28/2012
• Est. Priority Date: 06/18/2008
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Foley, John A.
• Primary Examiner(s): Bhatia, Ajay
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US12/214,283
• Time in Patent Office: 1,532 Days
• Field of Search: None
• US Class Current: 714/764
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.

Claims

1. An apparatus, comprising:

a memory including an error detection system (EDS) to detect an error event in the memory, where the error event involves at least one bit in the memory changing state erroneously;

a scrub logic to scrub the memory to correct an error in the memory; and

a scrub rate adaptive logic (SRAL) to selectively control a memory scrub frequency associated with the scrub logic based, at least in part, on a number of error events detected by the EDS during an error checking interval (ECI), wherein a duration of the ECI is varied based on the memory scrub frequency.

2. The apparatus of claim 1, where the SRAL is to increase the memory scrub frequency by a scrub rate delta upon detecting that a number of error events exceeds a dynamic random access memory (DRAM) error threshold during a threshold window ECI, and where the memory scrub frequency is limited to a maximum frequency.

3. The apparatus of claim 2, where the scrub rate delta is dynamically, automatically configurable based, at least in part, on a scrub rate delta change rate, where the scrub rate delta is the change in the memory scrub frequency.

4. The apparatus of claim 2, where the DRAM error threshold is dynamically, automatically configurable based, at least in part, on a DRAM error threshold change rate.

5. The apparatus of claim 1, where the SRAL is to decrease the memory scrub frequency by a scrub rate delta upon detecting a number of error events that are less than a minimum error threshold amount during a scrub retry period ECI, and where the memory scrub frequency is limited to a minimum frequency.

6. The apparatus of claim 1, where a scrub rate delta has a first value when used for increasing the memory scrub frequency and a second value when used for decreasing the memory scrub frequency.

7. The apparatus of claim 1, where the memory is an error corrective code (ECC) memory that includes the EDS.

8. The apparatus of claim 7, where the ECC memory includes ECC data bits.

9. The apparatus of claim 1, where the error event is one of, a single event upset (SEU) that includes a single bit in an addressable unit of memory in the memory changing state erroneously during the ECI, and a multiple event upset (MEU) in the memory that includes multiple bits in an addressable unit of memory in the memory changing state erroneously during the ECI.

10. The apparatus of claim 1, where the apparatus is to operate in a space vehicle located above one hundred kilometers from the surface of the earth.

11. The apparatus of claim 1, where the apparatus is to operate at one or more of, above the surface of the earth, underground, and underwater.

12. The apparatus of claim 1, where the EDS employs one or more of, a single bit Hamming error detection scheme, and a multiple bit Reed-Solomon error detection scheme, and where the scrub logic employs one or more of, a single bit Hamming error correction scheme, and a multiple bit Reed-Solomon error correction scheme.

13. The apparatus of claim 1, where the SRAL partitions the memory and selectively scrubs a memory partition based on the location of error events in the memory and a scrub priority of the memory partition, where the scrub priority of the memory partition depends on a pre-defined memory status.

14. Logic encoded in one or more non-transitory computer-readable media for execution and when executed operable to perform a method, the method comprising:

establishing a memory scrub frequency for a memory;

establishing an error checking interval (ECI) during which a number of error events in the memory are to be counted to determine whether the memory scrub frequency will be modified, wherein a duration of the ECI is varied based on the memory scrub frequency;

totaling the number of errors detected during the ECI;

selectively decreasing the memory scrub frequency by a first scrub rate delta upon determining that a number of error events that occurred during the ECI are less than a minimum error threshold amount; and

selectively increasing the memory scrub frequency by a second scrub rate delta upon determining that a number of error events that occurred during the ECI are greater than a maximum error threshold amount.

15. The logic of claim 14, where the memory scrub frequency is limited by a maximum memory scrub frequency and by a minimum memory scrub frequency.

16. The logic of claim 14, where the ECI is adjusted based, at least in part, upon the number of error events detected during a previous ECI.

17. The logic of claim 14, where the memory scrub frequency is changed in response to detecting a threshold number of error events occurring during a set of ECIs.

18. The logic of claim 14, where the scrub rate delta is changed in response to detecting a threshold number of error events occurring during a set of ECIs and where the ECI is changed in response to detecting a threshold number of error events occurring during the set of ECIs.

19. The logic of claim 14, where a plurality of ECIs and a plurality of thresholds are utilized concurrently, where a first ECI and a first error threshold are utilized to initiate an immediate memory scrub, and where a second ECI and a second error threshold are utilized to change the memory scrub frequency.

20. A system, comprising:

means for detecting an error event in a memory, where the error event involves at least one bit in the memory changing state erroneously;

means for scrubbing the memory, where scrubbing the memory corrects errors in the memory; and

means for determining whether to change a scrub frequency of the memory based, at least in part, on a number of error events during an error checking interval (ECI), wherein a duration of the ECI is varied based on the memory scrub frequency.