Exploiting independent portions of logic designs for timing optimization
First Claim
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1. A method of implementing an electronic design, comprising:
- receiving a design for implementation on an electronic device;
generating a timing graph including a plurality of edges with associated timing data, the timing graph generated using a processor;
identifying a first relaxation group comprising a first plurality of edges in a clock domain, wherein identifying the first relaxation group comprises;
identifying a first edge having a low slack or slack ratio;
traversing the timing graph from the first edge through a first plurality of search paths until a second edge having a high slack or slack ratio is identified, wherein the high slack or slack ratio corresponds to a slack threshold, wherein the slack threshold is selected from the group consisting of an absolute threshold, based on the achieved or required clock period, and a function of the slack ratio of the initial edge being expanded from to guide the search to find a relatively non-critical boundary; and
designating the plurality of edges in the first plurality of search paths from the first edge to the second edge as edges in the first relaxation group;
identifying a second relaxation group comprising a second plurality of edges in the clock domain; and
independently relaxing the timing data corresponding to the first plurality of edges and the timing data corresponding to the second plurality of edges during design optimization.
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Abstract
Slacks or timing weights are determined during implementation of an electronic design to improve design optimization. Multiple failings paths are optimized simultaneously by generalizing the notion of constraint relaxation used when computing slacks and timing weights to apply to portions of the design that can be independently optimized, rather than strictly adhering to clock domains and other coupled timing constraints used by conventional relaxation-based approaches. Improved calculation of slacks or timing weights better guides optimization algorithms.
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Citations
24 Claims
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1. A method of implementing an electronic design, comprising:
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receiving a design for implementation on an electronic device; generating a timing graph including a plurality of edges with associated timing data, the timing graph generated using a processor; identifying a first relaxation group comprising a first plurality of edges in a clock domain, wherein identifying the first relaxation group comprises; identifying a first edge having a low slack or slack ratio; traversing the timing graph from the first edge through a first plurality of search paths until a second edge having a high slack or slack ratio is identified, wherein the high slack or slack ratio corresponds to a slack threshold, wherein the slack threshold is selected from the group consisting of an absolute threshold, based on the achieved or required clock period, and a function of the slack ratio of the initial edge being expanded from to guide the search to find a relatively non-critical boundary; and designating the plurality of edges in the first plurality of search paths from the first edge to the second edge as edges in the first relaxation group; identifying a second relaxation group comprising a second plurality of edges in the clock domain; and independently relaxing the timing data corresponding to the first plurality of edges and the timing data corresponding to the second plurality of edges during design optimization. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An apparatus comprising:
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an interface configured to receive a design for implementation on an electronic device; a processor configured to generate a timing graph including a plurality of edges corresponding to a plurality of slack or slack ratios, the timing graph generated using a processor, and identify a first edge having a low slack or slack ratio; wherein the processor is further configured to traverse the timing graph from the first edge through a first plurality of search paths until a second edge having a high slack or slack ratio is identified, wherein the high slack or slack ratio corresponds to a slack threshold wherein the slack threshold is selected from the group consisting of an absolute threshold, based on the achieved or required clock period, and a function of the slack ratio of the initial edge being expanded from to guide the search to find a relatively non-critical boundary, and designate the plurality of edges in the first plurality of search paths from the first edge to the second edge as edges in a first relaxation group.
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24. A method of implementing an electronic design, comprising:
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receiving a design for implementation on an electronic device; generating a timing graph including a plurality of edges with associated timing data, the timing graph generated using a processor; identifying a first relaxation group comprising a first plurality of edges in a clock domain; identifying a second relaxation group comprising a second plurality of edges in the clock domain; and independently relaxing the timing data corresponding to the first plurality of edges and the timing data corresponding to the second plurality of edges during design optimization; wherein a plurality of mutually exclusive relaxation groups including the first relaxation group, the second relaxation group, and a third relaxation group are identified.
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Specification