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Exploiting independent portions of logic designs for timing optimization

  • US 8,255,860 B1
  • Filed: 03/31/2010
  • Issued: 08/28/2012
  • Est. Priority Date: 04/03/2009
  • Status: Active Grant
First Claim
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1. A method of implementing an electronic design, comprising:

  • receiving a design for implementation on an electronic device;

    generating a timing graph including a plurality of edges with associated timing data, the timing graph generated using a processor;

    identifying a first relaxation group comprising a first plurality of edges in a clock domain, wherein identifying the first relaxation group comprises;

    identifying a first edge having a low slack or slack ratio;

    traversing the timing graph from the first edge through a first plurality of search paths until a second edge having a high slack or slack ratio is identified, wherein the high slack or slack ratio corresponds to a slack threshold, wherein the slack threshold is selected from the group consisting of an absolute threshold, based on the achieved or required clock period, and a function of the slack ratio of the initial edge being expanded from to guide the search to find a relatively non-critical boundary; and

    designating the plurality of edges in the first plurality of search paths from the first edge to the second edge as edges in the first relaxation group;

    identifying a second relaxation group comprising a second plurality of edges in the clock domain; and

    independently relaxing the timing data corresponding to the first plurality of edges and the timing data corresponding to the second plurality of edges during design optimization.

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