3D semiconductor device

• US 8,258,810 B2
• Filed: 09/30/2010
• Issued: 09/04/2012
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Ze'ev
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): Hammond, Crystal L
• Application Number:
  US12/894,252
• Publication Number:
  US 20120194218A1
• Time in Patent Office: 705 Days
• Field of Search: None
• US Class Current: 326/39
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.

Claims

1. A semiconductor device, comprising:

a first transistor layer; and

a second transistor layer three dimensionally overlaying the first transistor layer where each layer comprises a single monocrystalline structure, wherein said first transistor layer comprises a plurality of flip-flops each having an additional signal selectively coupleable to its input or output, said signal generated by said second transistor layer, said semiconductor device further including first logic circuits of the first transistor layer selectively replaceable by second logic circuits of the second transistor layer.

2. A semiconductor device according to claim 1, wherein said selectively coupleable additional input comprises multiplexer.

3. A semiconductor device according to claim 2, further comprising a programmable element to control said multiplexer.

4. A semiconductor device according to claim 1, further comprising a controller to perform testing of a portion of said device and to control said selectively replaceable.

5. A semiconductor device according to claim 1, further comprising a signal coupled from each of said flip-flop outputs to the second transistor layer.

6. A semiconductor device according to claim 1, wherein each of said flip-flops are fed by a logic cone of the same layer and wherein the logic the respectful logic cone comprising said second transistors, is logically equivalent to the logic cone comprising first transistors.

7. A semiconductor device according to claim 1, further comprising a plurality of circuits each performing a comparison between a signal generated by transistors of the first transistor layer and a signal generated by transistors of the second transistor layer.

8. A semiconductor device, comprising:

a first transistor layer; and

a second transistor layer three dimensionally overlaying the first transistor layer where each layer comprises a single monocrystalline structure, wherein said first transistor layer comprises a plurality of sequential cells according to a net-list, and wherein each sequential cell has an additional signal selectively coupleable to its input or output, said signal generated by said second transistor layer, said semiconductor device further including first logic circuits of the first transistor layer selectively replaceable by second logic circuits of the second transistor layer.

9. A semiconductor device according to claim 8, comprising a plurality of multiplexers each configured to selectively replace a signal generated by the output of a sequential element of the plurality of sequential elements by a signal generated by transistors of the second transistor layer.

10. A semiconductor device according to claim 8, further comprising a controller to perform testing of a portion of said device.

11. A semiconductor device according to claim 8, further comprising a plurality of signals generated by said second transistor layer coupled to a plurality multiplexers, each multiplexer having an output coupled to a sequential cell of said first transistors layer.

12. A semiconductor device according to claim 8, further comprising a logic circuit comprising transistors of the first transistor layer selectively replaceable by a logic circuit comprising transistors of the second transistor layer.

13. A semiconductor device according to claim 8, further comprising a plurality of circuits each comparing a signal generated by transistors of the first transistor layer and a signal generated by transistors of the second transistor layer.

14. A semiconductor device, comprising:

a first transistor layer,

a second transistor layer three dimensionally overlaying the first transistor layer where each layer is fabricated as a single monocrystalline structure, including first logic circuits of the first transistor layer selectively replaceable by second logic circuits of the second transistor layer, and

metal interconnect to form a logic circuit comprising transistors of said second transistor layer, wherein said metal interconnect is defined by direct-write-ebeam.

15. A semiconductor device according to claim 14, further comprising a plurality of flip-flops each having a multiplexer coupled to its input, wherein one of said multiplexer inputs is coupled to said second transistor layer.

16. A semiconductor device according to claim 14, further comprising a plurality of sequential cells according to a net-list, wherein each sequential cell has an extra signal from its output coupled to a logic circuit comprising transistors of second transistor layer.

17. A semiconductor device according to claim 14, further comprising a controller to perform testing of a portion of said device.

18. A semiconductor device according to claim 14, further comprising a signal from said logic circuit is coupled to a multiplexer having an output coupled to a to flip-flop comprising transistors of the first transistor layer.

19. A semiconductor device according to claim 14, further comprising a logic circuit comprising transistors of the first transistor layer replaced by logic comprising transistors of the second transistor layer.