Semiconductor memory device and semiconductor device
First Claim
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1. A semiconductor memory device comprising:
- a plurality of data hold memory cells;
an initialization memory cell;
a first data line;
a second data line; and
a word line,wherein each of the plurality of data hold memory cells and the initialization memory cell comprises;
a first inverter circuit comprising a first transistor;
a second inverter circuit comprising a second transistor;
a third transistor; and
a fourth transistor,wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor,wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line,wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line,wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell andwherein the plurality of data hold memory cells and the initialization memory cell are electrically connected through the word line.
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Abstract
The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.
48 Citations
19 Claims
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1. A semiconductor memory device comprising:
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a plurality of data hold memory cells; an initialization memory cell; a first data line; a second data line; and a word line, wherein each of the plurality of data hold memory cells and the initialization memory cell comprises; a first inverter circuit comprising a first transistor; a second inverter circuit comprising a second transistor; a third transistor; and a fourth transistor, wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line, wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line, wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell and wherein the plurality of data hold memory cells and the initialization memory cell are electrically connected through the word line. - View Dependent Claims (8, 12, 16)
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2. A semiconductor memory device comprising:
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a plurality of data hold memory cells; an initialization memory cell; a first data line; a second data line; and a word line, wherein each of the plurality of data hold memory cells and the initialization memory cell comprises; a first inverter circuit comprising a first transistor; a second inverter circuit comprising a second transistor; a third transistor; and a fourth transistor, wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line, wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line, wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor, wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and wherein the plurality of data hold memory cells and the initialization memory cell are electrically connected through the word line. - View Dependent Claims (5, 9, 13, 17)
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3. A semiconductor memory device comprising:
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a plurality of data hold memory cells; an initialization memory cell; a first data line; a second data line; a third data line; a word line; and a ground line, wherein each of the plurality of data hold memory cells and the initialization memory cell comprises; a first inverter circuit comprising a first transistor; a second inverter circuit comprising a second transistor; a third transistor electrically connected to the ground line; and a fourth transistor electrically connected to the third transistor, wherein a gate electrode of the fourth transistor is electrically connected to the word line, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit, the second data line, and a gate electrode of the third transistor, wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line, wherein the second inverter circuit is electrically connected to the third data line through the third transistor and the fourth transistor, wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor, and wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and wherein the plurality of data hold memory cells and the initialization memory cell are electrically connected through the word line. - View Dependent Claims (6, 10, 14, 18)
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4. A semiconductor memory device comprising:
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a plurality of data hold memory cells; an initialization memory cell; a first data line; a second data line; a third data line; a word line; and a power supply line, wherein each of the plurality of data hold memory cells and the initialization memory cell comprises; a first inverter circuit comprising a first transistor, wherein the first inverter circuit is electrically connected to the power supply line; a second inverter circuit comprising a second transistor, wherein the second inverter circuit is electrically connected to the power supply line; a third transistor; and a fourth transistor electrically connected to the third transistor, wherein a gate electrode of the fourth transistor is electrically connected to the word line, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and a gate electrode of the third transistor, wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line, wherein the second data line is electrically connected to the input terminal of the first inverter circuit and the output terminal of the second inverter circuit, wherein the power supply line is electrically connected to the third data line through the third transistor and the fourth transistor, wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor, and wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and wherein the plurality of data hold memory cells and the initialization memory cell are electrically connected through the word line. - View Dependent Claims (7, 11, 15, 19)
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Specification