Random number generator with ring oscillation circuit

• US 8,260,835 B2
• Filed: 08/18/2008
• Issued: 09/04/2012
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation, Renesas System Design, Co., Ltd. (Renesas Electronics Corporation)
• Inventors: Fukushima, Kazuhiko, Yamaguchi, Atsuo
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US12/193,105
• Publication Number:
  US 20080313249A1
• Time in Patent Office: 1,478 Days
• Field of Search: None
• US Class Current: 708/251
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop'"'"'s delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Claims

1. A semiconductor apparatus comprising:

a central processing unit;

a ring oscillator including plural gate circuits; and

a counter circuit,

wherein the central processing unit supplies a first signal to the ring oscillator for instructing to start an oscillation, and

the counter circuit counts a number of output signals from the plural gate circuits during a period, which is determined by a time when a metastable state disappears in the ring oscillator, after the ring oscillator receives the first signal.

2. The semiconductor apparatus according to claim 1,

wherein the number of the plural gate circuits is an odd number.

3. The semiconductor apparatus according to claim 2,

wherein the counter circuit includes plural flip flop gates, a clock terminal of each of which couples to the output of a corresponding gate circuit of the ring oscillator.

4. The semiconductor apparatus according to claim 1 using the number of the output signals as a random number.