Memory controllers, memory systems, solid state drives and methods for processing a number of commands

• US 8,260,973 B2
• Filed: 09/23/2011
• Issued: 09/04/2012
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Liao, Yu-Song, Yang, Jui-Yao, Nemazie, Siamack
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US13/242,535
• Publication Number:
  US 20120011335A1
• Time in Patent Office: 347 Days
• Field of Search: None
• US Class Current: 710/6
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Claims

1. A memory controller, comprising:

a plurality of back end channels, each back end channel corresponding to a different memory device; and

a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of read commands,

wherein the front end command dispatcher is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands such that fewer commands are sent to accomplish the same net read from memory in order to economize distribution of the number of read commands among the plurality of back end channels.

2. The memory controller of claim 1, wherein the front end command dispatcher includes a command processor portion configured to modify one or more commands so as to economize distribution of the commands among the plurality of back end channels, and a dispatcher portion configured to distribute commands among the plurality of back end channels.

3. The memory controller of claim 1, wherein the front end command dispatcher is configured to perform host command integrity checking in hardware.

4. The memory controller of claim 1, including a front end processor (FEP) communicatively coupled to the plurality of back end channels,

wherein the FEP is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands in order to economize distribution of the number of read commands among the plurality of back end channels.

5. A memory controller, comprising:

a plurality of back end channels, each back end channel corresponding to a different memory device; and

a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of read commands,

wherein the front end command dispatcher is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands such that fewer commands are sent to accomplish the same net read from memory in order to economize distribution of the number of read commands among the plurality of back end channels.

6. A memory controller, comprising:

a plurality of back end channels, each back end channel corresponding to a different memory device; and

a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of write commands,

wherein the front end command dispatcher is configured to determine a net change to memory to be accomplished by the number of write commands, and to modify one or more of the number of write commands such that fewer commands are sent to accomplish the same net change to the memory in order to economize distribution of the number of write commands among the plurality of back end channels.

7. The memory controller of claim 6, wherein the command dispatcher is configured to modify the one or more of the number of write commands in order to economize distribution only when the plurality of back end channels are busy.

8. The memory controller of claim 6, wherein the command dispatcher is configured to not distribute one of the number of write commands from the command queue without changing the determined net change to memory by the number of write commands.

9. The memory controller of claim 8, wherein the command dispatcher is configured to modify a memory range associated with a first write command in the command queue to include a portion of the memory range of a second write command in the command queue, and thereafter not distribute the second write command from the command queue without changing the determined net change to memory by the number of write commands.

10. The memory controller of claim 6, wherein the number of write commands are received in the command queue in an initial order, and the command dispatcher is configured to change an order of the number of write commands in the command queue from the initial order to a changed order.

11. The memory controller of claim 10, wherein the command dispatcher is configured to distribute commands according to the changed order of the number of write commands in the command queue rather than according to the initial order.

12. The memory controller of claim 6, wherein the command dispatcher is configured to modify at least one of the number of write commands in the command queue by combining commands to overlapping memory locations.

13. The memory controller of claim 12, wherein the command dispatcher is configured to change an order of the number of write commands in the command queue to a changed order in response to at least one of the number of write commands being modified.

14. The memory controller of claim 12, wherein the command dispatcher is configured to not distribute a write command determined to involve a number of memory locations that will be overwritten by a write command to be subsequently-executed in the command queue.

15. The memory controller of claim 12, wherein the command dispatcher is configured to not execute a write command determined to involve the number of memory locations that will be overwritten by a subsequently-executed write command without an intervening read operation involving the number of memory locations.

16. The memory controller of claim 12, wherein the command dispatcher is configured to group multiple write commands into a single write command.

17. The memory controller of claim 16, wherein the command dispatcher is configured to determine that at least two write commands are a same operation involving logically adjacent memory locations, and combine the at least two write commands into a single write command involving the logically adjacent memory locations.

18. The memory controller of claim 16, wherein the command dispatcher is configured to determine that at least two write commands are a same operation involving logically overlapping memory locations, and combine the at least two write commands into a single write command involving the logically overlapping memory locations.

19. The memory controller of claim 6, wherein the payload associated with a particular write command is distributed among more than one of the plurality of back end channels, and the command dispatcher is configured to distribute the particular write command to each of the more than one of the plurality of back end channels.

20. The memory controller of claim 19, wherein the command dispatcher is configured to determine an associated logical block address and sector count for a portion of the payload associated with each of the more than one of the plurality of back end channels, and modify the particular write command distributed to a respective back end channel with the logical block address and sector count for the associated portion of the payload.

21. The memory controller of claim 6, wherein the command dispatcher is configured to modify write commands in the command queue during a time when the command dispatcher is prevented from distributing commands to the plurality of back end channels.