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Memory controllers, memory systems, solid state drives and methods for processing a number of commands

  • US 8,260,973 B2
  • Filed: 09/23/2011
  • Issued: 09/04/2012
  • Est. Priority Date: 04/09/2009
  • Status: Active Grant
First Claim
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1. A memory controller, comprising:

  • a plurality of back end channels, each back end channel corresponding to a different memory device; and

    a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of read commands,wherein the front end command dispatcher is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands such that fewer commands are sent to accomplish the same net read from memory in order to economize distribution of the number of read commands among the plurality of back end channels.

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